IR3084UMTRPBF International Rectifier, IR3084UMTRPBF Datasheet - Page 20

• Manufacturer Part Number: IR3084UMTRPBF
• Description: IC CTLR XPHASE 28-MLPQ
• Manufacturer: International Rectifier
• Series: XPhase™r

Specifications of IR3084UMTRPBF

• Package / Case: 28-MLPQ
• Mounting Type: Surface Mount
• Current - Supply: 14mA
• Voltage - Supply: 9.5 V ~ 16 V
• Operating Temperature: 0°C ~ 100°C
• Applications: Processor
• Package: 28-Lead MLPQ
• Circuit: X-Phase Control IC
• Switch Freq (khz): 150kHz to 1.0MHz
• Pbf: PbF Option Available
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 10a depicts the start-up sequence without AVP in Boot mode − the VIDSEL pin is either grounded or
floated. First, the VDAC pin is charged to the 1.1V Boot voltage. Then, if there are no fault conditions, the
SS/DEL capacitor will begin to be charged. Initially, the error amplifier’s output will be clamped low until the
voltage at the SS/DEL reaches 1.3V. After the voltage at the SS/DEL pin rises to 1.3V, the error amplifier’s
output will begin to rise and the converter’s output voltage will be regulated 1.3V below the voltage at the SS/DEL
pin. The converter’s output voltage will slowly ramp to the 1.1V Boot voltage. The SS/DEL voltage will continue
to increase until it rises above the 3.10V threshold of the VID delay comparator. When the SS/DEL voltage
exceeds 3.10V, the VID inputs will be sampled and the VDAC pin will transition to the level determined by the VID
inputs at the dynamic VID slew rate. When the voltage on the SS/DEL pin rises above 3.77V the VRRDY Delay
Comparator will allow the VRRDY signal to be asserted. SS/DEL will continue to rise until finally settling at
3.85V, indicating the end of the start-up sequence.
Figure 10b depicts the start-up sequence in Opteron/Athlon64 mode − VIDSEL is connected to GND via a 6.49K
resistor. First, the external VID setting is sampled and the VDAC pin is set to the desired VID voltage. Then, if
there are no fault conditions, the SS/DEL capacitor will begin to charge. Initially, the error amplifier’s output will
be clamped low until the voltage at the SS/DEL rises to 1.3V. After the voltage at the SS/DEL pin reaches 1.3V,
the error amplifier’s output will begin to rise and the converter’s output voltage will be regulated 1.3V below the
voltage at the SS/DEL pin. As the voltage at the SS/DEL pin continues to rise, the converter’s output voltage will
slowly increase until it is equal to the voltage at the VDAC pin. When the voltage on the SS/DEL pin rises above
3.77V the VRRDY Delay Comparator will allow the VRRDY signal to be asserted. SS/DEL will continue to rise
until finally settling at 3.85V, indicating the end of the start-up sequence.
If AVP is used, the soft start timing will change slightly because of the resistor from the VDRP amplifier to the
Error Amplifier’s FB pin. During startup with AVP, the VDRP amplifier will produce a voltage at the FB pin equal
to VDAC times the resistor divider formed by the droop resistor and the feedback resistor from Vcore to the FB
pin. To offset the contribution from the VDRP amplifier, the voltage at the SS/DEL pin will have to rise to beyond
1.3V before the Error Amplifier’s output and Vcore begin to rise. For a DAC setting of 1.3V with typical VR11
AVP, the Error Amplifier’s output will begin to rise when the voltage at the SS/DEL pin reaches approximately
1.8V. The effect of this offset will be to slightly lengthen the Start Delay (TD1) and shorten the Soft Start Ramp
Time (TD2).
The following table summarizes the differences between the 3 modes associated with setting the VIDSEL pin. In
addition to changing the soft start sequence, the NO_CPU code may or may not be ignored during startup and
the NO_CPU code may or may not be latched.
(0.9V<VIDSEL<1.7V)
Page 20 of 47
6.49K to GND
VIDSEL
Voltage
(<0.6V)
(>1.8V)
FLOAT
GND
Table 4: Controller Functionality versus VIDSEL Voltages
Opteron/Athlon64
Table
VR10
VR11
VID
Voltage During
1.1V Boot
Startup?
YES
YES
NO
Ignore NO CPU
Codes During
Startup?
YES
YES
NO
Latch NO CPU
Fault Code?
IR3084U
YES
YES
NO
9/14/2005