MC33912BAC Freescale Semiconductor, MC33912BAC Datasheet - Page 38

• Manufacturer Part Number: MC33912BAC
• Description: IC SYSTEM BASIS CHIP 32LQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC33912BAC

• Applications: System Basis Chip
• Current - Supply: 4.5mA
• Voltage - Supply: 5.5 V ~ 27 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 32-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

33912 SPI INTERFACE AND CONFIGURATION
link between a microcontroller (master) and the 33912.
transfer is prepared.
transfer and puts the MISO in the low-impedance state and
latches the analog status data (Register read data).
moved to MISO/MOSI pins. With the falling edge of the SPI
clock (SCLK), the data is sampled by the receiver.
edges are present during the active (low) phase of
38
33912
FUNCTIONAL DEVICE OPERATIONS
LOGIC COMMANDS AND REGISTERS
The serial peripheral interface creates the communication
The interface consists of four pins (see
•
• MOSI — Master-out Slave-in
During the inactive phase of the
The falling edge of the
With the rising edge of the SPI clock (SCLK), the data is
The data transfer is only valid if exactly 8 sample clock
CS
— Chip Select
Rising: 33912 changes MISO/
SCLK
MOSI
MISO
CS
Read Data Latch
MCU changes MOSI
CS
indicates the start of a new data
CS
(HIGH), the new data
LOGIC COMMANDS AND REGISTERS
Figure
VMS LINS HSS
A3
Falling: 33912 samples MOSI/
MCU samples MISO
20):
A2
CS
Figure 20. SPI Protocol
.
A1
Register Read Data
Register Write Data
A0
LSS
The master sends 4 bits of address (A3:A0) + 4 bits of control
information (C3:C0) and the slave replies with 4 system
status bits (VMS,LINS,HSS,LSS) + 4 bits of status
information (S3:S0).
the transfer and latches the write data (MOSI) into the
register. The
state.
condition. Reset condition is the condition causing the bit to
be set to its reset value. The main reset conditions are:
reset and BATFAIL flag sets.
C3
S3
• MISO — Master-in Slave-out
• SCLK— Serial Clock
A complete data transfer via the SPI consists of 1 byte.
The rising edge of the Chip Select
Register reset values are described along with the reset
- Power-On Reset (POR): the level at which the logic is
- Reset mode
- Reset done by the RST pin (ext_reset)
C2
S2
CS
C1
S1
high forces MISO to the high-impedance
C0
S0
Analog Integrated Circuit Device Data
Write Data Latch
Freescale Semiconductor
CS
indicates the end of