MAX16066ETL+ Maxim Integrated Products, MAX16066ETL+ Datasheet - Page 11

• Manufacturer Part Number: MAX16066ETL+
• Description: IC SYSTEM MANAGER 8CH 40-TQFN
• Manufacturer: Maxim Integrated Products

Specifications of MAX16066ETL+

• Applications: Power Supply Monitor, Sequencer
• Voltage - Supply: 2.8 V ~ 14 V
• Current - Supply: 4.5mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 40-VQFN Exposed Pad, 40-HVQFN, 40-SQFN, 40-DHVQFN
• Number Of Voltages Monitored: 8
• Undervoltage Threshold: 2.7 V
• Manual Reset: Resettable
• Watchdog: Yes
• Battery Backup Switching: No
• Power-up Reset Delay (typ): 200 us
• Supply Voltage (max): 14 V
• Supply Voltage (min): 2.8 V
• Supply Current (typ): 10 mA
• Maximum Power Dissipation: 2105 mW
• Mounting Style: SMD/SMT
• Maximum Operating Temperature: + 85 C
• Chip Enable Signals: No
• Internal Hysteresis: Yes
• Minimum Operating Temperature: - 40 C
• Power Fail Detection: No
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Input: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

The MAX16065 manages up to twelve system power
supplies and the MAX16066 can manage up to eight
system power supplies. After boot-up, if EN is high and
the software enable bit is set to ‘1,’ a power-up sequence
begins based on the configuration stored in flash and
the EN_OUT_s are controlled accordingly. When the
power-up sequence is successfully completed, the
monitoring phase begins. An internal multiplexer cycles
through each MON_ input. At each multiplexer stop, the
10-bit ADC converts the monitored analog voltage to a
digital result and stores the result in a register. Each time
a conversion cycle (50Fs, max) completes, internal logic
circuitry compares the conversion results to the over-
voltage and undervoltage thresholds stored in memory.
When a result violates a programmed threshold, the
conversion can be configured to generate a fault. GPIO_
can be programmed to assert on combinations of faults.
Additionally, faults can be configured to shut off the sys-
tem and trigger the nonvolatile fault logger, which writes
all fault information automatically to the flash and write-
protects the data to prevent accidental erasure.
The MAX16065/MAX16066 contain both SMBus and
JTAG serial interfaces for accessing registers and flash.
Use only one interface at any given time. For more infor-
mation on how to access the internal memory through
these interfaces, see the SMBus-Compatible Interface
and JTAG Serial Interface sections. The memory map
is divided into three pages with access controlled by
special SMBus and JTAG commands.
The factory-default values at POR (power-on reset) for all
RAM registers are ‘0’s. POR occurs when V
the undervoltage-lockout threshold (UVLO) of 2.8V (max).
At POR, the device begins a boot-up sequence. During
the boot-up sequence, all monitored inputs are masked
from initiating faults and flash contents are copied to
the respective register locations. During boot-up, the
MAX16065/MAX16066 are not accessible through the
serial interface. The boot-up sequence takes up to
150Fs, after which the device is ready for normal opera-
tion. RESET is asserted low up to the boot-up phase and
remains asserted for its programmed timeout period once
sequencing is completed and all monitored channels
are within their respective thresholds. Up to the boot-up
phase, the GPIO_s and EN_OUT_s are high impedance.
12-Channel/8-Channel, Flash-Configurable System
Managers with Nonvolatile Fault Registers
______________________________________________________________________________________
Detailed Description
CC
reaches
Apply 2.8V to 14V to V
MAX16066. Bypass V
tor. Two internal voltage regulators, ABP and DBP,
supply power to the analog and digital circuitry within
the device. For operation at 3.6V or lower, disable the
regulators by connecting ABP and DBP to V
ABP is a 3.0V (typ) voltage regulator that powers the inter-
nal analog circuitry. Bypass ABP to GND with a 1FF ceram-
ic capacitor installed as close to the device as possible.
DBP is an internal 3.0V (typ) voltage regulator. DBP
powers flash and digital circuitry. All push-pull outputs
refer to DBP. DBP supplies the input voltage to the inter-
nal charge pump when the programmable outputs are
configured as charge-pump outputs. Bypass the DBP
output to GND with a 1FF ceramic capacitor installed as
close as possible to the device.
Do not power external circuitry from ABP or DBP.
To sequence a system of power supplies safely, the
output voltage of a power supply must be good before
the next power supply may turn on. Connect EN_OUT_
outputs to the enable input of an external power supply
and connect MON_ inputs to the output of the power
supply for voltage monitoring. More than one MON_ can
be used if the power supply has multiple outputs.
The MAX16065/MAX16066 provide a system of ordered
slots to sequence multiple power supplies. To determine
the sequence order, assign each EN_OUT_ to a slot
ranging from Slot 1 to Slot 12. EN_OUT_(s) assigned to
Slot 1 are turned on first, followed by outputs assigned
to Slot 2, and so on through Slot 12. Multiple EN_OUT_s
assigned to the same slot turn on at the same time.
Each slot includes a built-in configurable sequence delay
(registers r77h to r7Dh) ranging from 20Fs to 1.6s. During
a reverse sequence, slots are turned off in reverse order
starting from Slot 12. The MAX16065/MAX16066 can be
configured to power-down in simultaneous mode or in
reverse sequence mode as set in r75h[0]. See Tables 5
and 6 for the EN_OUT_ slot assignment bits, and Tables
3 and 4 for the sequence delays.
During power-up or power-down sequencing, the cur-
rent sequencer state can be found in r21h[4:0].
CC
CC
to ground with a 10FF capaci-
to power the MAX16065/
Sequence Order
Sequencing
CC
.
Power
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