MAX16066ETL+ Maxim Integrated Products, MAX16066ETL+ Datasheet - Page 40

• Manufacturer Part Number: MAX16066ETL+
• Description: IC SYSTEM MANAGER 8CH 40-TQFN
• Manufacturer: Maxim Integrated Products

Specifications of MAX16066ETL+

• Applications: Power Supply Monitor, Sequencer
• Voltage - Supply: 2.8 V ~ 14 V
• Current - Supply: 4.5mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 40-VQFN Exposed Pad, 40-HVQFN, 40-SQFN, 40-DHVQFN
• Number Of Voltages Monitored: 8
• Undervoltage Threshold: 2.7 V
• Manual Reset: Resettable
• Watchdog: Yes
• Battery Backup Switching: No
• Power-up Reset Delay (typ): 200 us
• Supply Voltage (max): 14 V
• Supply Voltage (min): 2.8 V
• Supply Current (typ): 10 mA
• Maximum Power Dissipation: 2105 mW
• Mounting Style: SMD/SMT
• Maximum Operating Temperature: + 85 C
• Chip Enable Signals: No
• Internal Hysteresis: Yes
• Minimum Operating Temperature: - 40 C
• Power Fail Detection: No
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Input: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

12-Channel/8-Channel, Flash-Configurable System
Managers with Nonvolatile Fault Registers
Figure
over the bus is 8 bits long and is always followed by an
acknowledge pulse. SCL is a logic input, while SDA is
an open-drain input/output. SCL and SDA both require
external pullup resistors to generate the logic-high volt-
age. Use 4.7kI for most applications.
Each clock pulse transfers one data bit. The data on SDA
must remain stable while SCL is high (Figure 11); other-
wise the MAX16065/MAX16066 detect a START or STOP
condition (Figure 12) from the master. SDA and SCL idle
high when the bus is not busy.
Both SCL and SDA idle high when the bus is not busy.
A master device signals the beginning of a transmission
with a START condition by transitioning SDA from high to
low while SCL is high. The master device issues a STOP
condition by transitioning SDA from low to high while
SCL is high. A STOP condition frees the bus for another
transmission. The bus remains active if a REPEATED
START condition is generated, such as in the block read
protocol (see Figure 1).
The MAX16065/MAX16066 recognize a STOP condition
at any point during transmission except if a STOP condi-
tion occurs in the same high pulse as a START condition.
This condition is not a legal SMBus format; at least one
clock pulse must separate any START and STOP condition.
A REPEATED START can be sent instead of a STOP
condition to maintain control of the bus during a read
operation. The START and REPEATED START conditions
are functionally identical.
40
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SDA
SCL
11. Bit Transfer
DATA LINE STABLE,
DATA VALID
DATA ALLOWED
CHANGE OF
REPEATED START Conditions
START and STOP Conditions
Early STOP Conditions
Bit Transfer
Figure
The acknowledge bit (ACK) is the 9th bit attached to any
8-bit data word. The receiving device always generates
an ACK. The MAX16065/MAX16066 generate an ACK
when receiving an address or data by pulling SDA low
during the 9th clock period (Figure 13). When transmit-
ting data, such as when the master device reads data
back from the MAX16065/MAX16066, the device waits for
the master device to generate an ACK. Monitoring ACK
allows for detection of unsuccessful data transfers. An
unsuccessful data transfer occurs if the receiving device
is busy or if a system fault has occurred. In the event of an
unsuccessful data transfer, the bus master can reattempt
communication at a later time. The MAX16065/MAX16066
generate a NACK after the command byte received dur-
ing a software reboot, while writing to the flash, or when
receiving an illegal memory address.
Use the slave address input, A0, to allow multiple identi-
cal devices to share the same serial bus. Connect A0 to
GND, DBP (or an external supply voltage greater than
2V), SCL, or SDA to set the device address on the bus.
See Table 27 for a listing of all possible 7-bit addresses.
The slave address can also be set to a custom value by
loading the address into register r8Bh[6:0]. See Table
26. If r8Bh[6:0] is loaded with 00h, the address is set by
input A0. Do not set the address to 09h or 7Fh to avoid
address conflicts. The slave address setting takes effect
immediately after writing to the register.
The MAX16065/MAX16066 feature a PEC mode that is
useful for improving the reliability of the communication
bus by detecting bit errors. By enabling PEC, an extra
SDA
SCL
12. START and STOP Conditions
CONDITION
START
S
Packet Error Checking (PEC)
Slave Address
Acknowledge
CONDITION
STOP
P