MAX16066ETL+ Maxim Integrated Products, MAX16066ETL+ Datasheet - Page 12

• Manufacturer Part Number: MAX16066ETL+
• Description: IC SYSTEM MANAGER 8CH 40-TQFN
• Manufacturer: Maxim Integrated Products

Specifications of MAX16066ETL+

• Applications: Power Supply Monitor, Sequencer
• Voltage - Supply: 2.8 V ~ 14 V
• Current - Supply: 4.5mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 40-VQFN Exposed Pad, 40-HVQFN, 40-SQFN, 40-DHVQFN
• Number Of Voltages Monitored: 8
• Undervoltage Threshold: 2.7 V
• Manual Reset: Resettable
• Watchdog: Yes
• Battery Backup Switching: No
• Power-up Reset Delay (typ): 200 us
• Supply Voltage (max): 14 V
• Supply Voltage (min): 2.8 V
• Supply Current (typ): 10 mA
• Maximum Power Dissipation: 2105 mW
• Mounting Style: SMD/SMT
• Maximum Operating Temperature: + 85 C
• Chip Enable Signals: No
• Internal Hysteresis: Yes
• Minimum Operating Temperature: - 40 C
• Power Fail Detection: No
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Input: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

12-Channel/8-Channel, Flash-Configurable System
Managers with Nonvolatile Fault Registers
Table
The MAX16065/MAX16066 sequencing slots can be
split into two groups: the primary sequence and the sec-
ondary sequence. The last slot of the primary sequence
is selected using register bits r7Dh[7:4]. The secondary
sequence begins at the slot after the one specified in reg-
ister bits r7Dh[7:4]. The primary sequence is controlled
by the EN input and the software enable bit in r73h[0].
Outputs assigned to slots in the primary sequence turn
on, and monitoring begins for inputs assigned to these
slots. RESET deasserts after the primary sequence and
timeout period completes.
To initiate secondary sequencing and monitoring, set the
software enable r73h[1] bit to 1. Additionally, if GPIO_
is configured as EN2 then both the software enable 2
and EN2 must be high. Outputs assigned to slots in the
secondary sequence turn on, and monitoring begins for
inputs assigned to these slots. If a GPIO_ is configured
as the RESET2 output, it deasserts after the secondary
sequence and timeout period completes.
If a critical fault occurs in the primary sequence group,
both sequence groups automatically shut down. If a
critical fault occurs in the secondary sequence group,
then just the outputs assigned to slots in the second-
ary sequence turn off. The failing slot in secondary
sequence is stored in r1Dh.
12
REGISTER
ADDRESS
_____________________________________________________________________________________
21h
1. Current Sequencer Slot
BIT RANGE
[4:0]
[7:5]
Multiple Sequencing Groups
Current Sequencer State:
00000 = Slot 0
00001 = Slot 1
00010 = Slot 2
00011 = Slot 3
00100 = Slot 4
00101 = Slot 5
00110 = Slot 6
00111 = Slot 7
01000 = Slot 8
01001 = Slot 9
01010 = Slot 10
01011 = Slot 11
01100 = Slot 12
01101 = Secondary sequence monitoring mode
01110 = Primary sequence fault
01111 = Primary sequence monitoring mode
10000 = Secondary sequence fault
10001 to 11111 = Reserved
Reserved
Multiple sequencing groups can be used to conserve
power by powering down secondary systems when not
in use.
To initiate sequencing/tracking and enable monitoring,
the voltage at EN must be above 1.4V and the software
enable bit in r73h[0] must be set to ‘1.’ To power down
and disable monitoring, either pull EN below 1.35V or
set the Software Enable bit to ‘0.’ See Table 2 for the
software enable bit configurations. Connect EN to ABP
if not used.
If a fault condition occurs during the power-up cycle,
the EN_OUT_ outputs are powered down immediately,
regardless of the state of EN. In the monitoring state,
if EN falls below the threshold, the sequencing state
machine begins the power-down sequence. If EN rises
above the threshold during the power-down sequence,
the sequence state machine continues the power-down
sequence until all the channels are powered off and then
the device immediately begins the power-up sequence.
When in the monitoring state, a register bit, ENRESET,
is set to a ‘1’ when EN falls below the undervoltage
threshold. This register bit latches and must be cleared
through software. This bit indicates if RESET asserted
low due to EN going under the threshold. The POR state
of ENRESET is ‘0’. The bit is only set on a falling edge
DESCRIPTION
Enable and Enable2