MAX16066ETL+ Maxim Integrated Products, MAX16066ETL+ Datasheet - Page 37

• Manufacturer Part Number: MAX16066ETL+
• Description: IC SYSTEM MANAGER 8CH 40-TQFN
• Manufacturer: Maxim Integrated Products

Specifications of MAX16066ETL+

• Applications: Power Supply Monitor, Sequencer
• Voltage - Supply: 2.8 V ~ 14 V
• Current - Supply: 4.5mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 40-VQFN Exposed Pad, 40-HVQFN, 40-SQFN, 40-DHVQFN
• Number Of Voltages Monitored: 8
• Undervoltage Threshold: 2.7 V
• Manual Reset: Resettable
• Watchdog: Yes
• Battery Backup Switching: No
• Power-up Reset Delay (typ): 200 us
• Supply Voltage (max): 14 V
• Supply Voltage (min): 2.8 V
• Supply Current (typ): 10 mA
• Maximum Power Dissipation: 2105 mW
• Mounting Style: SMD/SMT
• Maximum Operating Temperature: + 85 C
• Chip Enable Signals: No
• Internal Hysteresis: Yes
• Minimum Operating Temperature: - 40 C
• Power Fail Detection: No
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Input: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Figure
Figure
The normal watchdog timeout period, t
the first transition on WDI before the conclusion of the
long startup watchdog period, t
During the normal operating mode, WDO asserts if the
FP does not toggle WDI with a valid transition (high-to-
low or low-to-high) within the standard timeout period,
t
RESET is asserted (Figure 9).
While EN is low, the watchdog timer is in reset. The
watchdog timer does not begin counting until the power-
on mode is reached and RESET is deasserted. The
watchdog timer is reset and WDO deasserts any time
RESET is asserted (Figure 10). The watchdog timer will
be held in reset while RESET is asserted.
12-Channel/8-Channel, Flash-Configurable System
WDI
. WDO remains asserted until WDI is toggled or
9. Watchdog Timer Operation
8. Normal Watchdog Startup Sequence
WDI
WDO
V
V
CC
0V
CC
0V
< t
Managers with Nonvolatile Fault Registers
______________________________________________________________________________________
WDI
< t
LAST MON_
WDI
RESET
WDI
< t
WDI
WDI_STARTUP
WDI
t
WDI
, begins after
t
RP
V
(Figure 8).
TH
> t
WDI
t
WDI_STARTUP
The watchdog can be configured to control the RESET
output as well as the WDO output. RESET asserts for
the reset timeout, t
and the Watchdog Reset Output Enable bit (r76h[7]) is
set to ‘1.’ When RESET is asserted, the watchdog timer
is cleared and WDO is deasserted, therefore, WDO
pulses low for a short time (approximately 1Fs) when
the watchdog timer expires. RESET is not affected by
the watchdog timer when the Watchdog Reset Output
Enable bit (r76h[7]) is set to ‘0.’ If a RESET is asserted
by the watchdog timeout, the WDRESET bit is set to ‘1.’ A
connected processor can check this bit to see the reset
was due to a watchdog timeout. See Table 24 for more
information on configuring watchdog functionality.
< t
WDI
< t
< t
WDI
RP
WDI
, when the watchdog timer expires
< t
WDI
< t
WDI
37