LM86CIMM National Semiconductor, LM86CIMM Datasheet - Page 8

• Manufacturer Part Number: LM86CIMM
• Description: IC DIODE/DGTL TEMP SENSOR 8-MSOP
• Manufacturer: National Semiconductor

Specifications of LM86CIMM

• Function: Hardware Monitor
• Topology: ADC (Sigma Delta), Comparator, Register Bank
• Sensor Type: External & Internal
• Sensing Temperature: 0°C ~ 85°C, External Sensor
• Output Type: SMBus™
• Output Alarm: Yes
• Output Fan: Yes
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 8-TSSOP, 8-MSOP (0.118", 3.00mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: LM86CIMMTR

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1.0 Functional Description
no longer present, the ALERT is de-asserted (Figure 3). For
example, if the ALERT output was activated by the compari-
son of LT
ALERT will return HIGH. This mode allows operation without
software intervention, once all registers are configured dur-
ing set-up. In order for the ALERT to be used as a tempera-
ture comparator, bit D0 (the ALERT configure bit) in the
FILTER and ALERT CONFIGURE REGISTER (xBF) must
be set high. This is not the power on default default state.
1.2.2 ALERT Output as an Interrupt
The LM86’s ALERT output can be implemented as a simple
interrupt signal when it is used to trigger an interrupt service
routine. In such systems it is undesirable for the interrupt flag
to repeatedly trigger during or before the interrupt service
routine has been completed. Under this method of operation,
during a read of the STATUS REGISTER the LM86 will set
the ALERT mask bit (D7 of the Configuration register) if any
bit in the STATUS REGISTER is set, with the exception of
Busy (D7) and OPEN (D2). This prevents further ALERT
triggering until the master has reset the ALERT mask bit, at
the end of the interrupt service routine. The STATUS REG-
ISTER bits are cleared only upon a read command from the
master (see Figure 4) and will be re-asserted at the end of
the next conversion if the triggering condition(s) persist(s). In
order for the ALERT to be used as a dedicated interrupt
signal, bit D0 (the ALERT configure bit) in the FILTER and
ALERT CONFIGURE REGISTER (xBF) must be set low.
This is the power on default state.
The following sequence describes the response of a system
that uses the ALERT output pin as a interrupt flag:
1. Master Senses ALERT low
2. Master reads the LM86 STATUS REGISTER to deter-
3. LM86 clears STATUS REGISTER, resets the ALERT
4. Master attends to conditions that caused the ALERT to
5. Master resets the ALERT mask (D7 in the Configuration
FIGURE 3. ALERT Comparator Temperature Response
mine what caused the ALERT
HIGH and sets the ALERT mask bit (D7 in the Configu-
ration register).
be triggered. The fan is started, setpoint limits are ad-
justed, etc.
register).
>
LHS, when this condition is no longer true the
Diagram
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(Continued)
8
1.2.3 ALERT Output as an SMBus ALERT
When the ALERT output is connected to one or more ALERT
outputs of other SMBus compatible devices and to a master,
an SMBus alert line is created. Under this implementation,
the LM86’s ALERT should be operated using the ARA (Alert
Response Address) protocol. The SMBus 2.0 ARA protocol,
defined in the SMBus specification 2.0, is a procedure de-
signed to assist the master in resolving which part generated
an interrupt and service that interrupt while impeding system
operation as little as possible.
The SMBus alert line is connected to the open-drain ports of
all devices on the bus thereby AND’ing them together. The
ARA is a method by which with one command the SMBus
master may identify which part is pulling the SMBus alert line
LOW and prevent it from pulling it LOW again for the same
triggering condition. When an ARA command is received by
all devices on the bus, the devices pulling the SMBus alert
line LOW, first, send their address to the master and second,
release the SMBus alert line after recognizing a successful
transmission of their address.
The SMBus 1.1 and 2.0 specification state that in response
to an ARA (Alert Response Address) “after acknowledging
the slave address the device must disengage its SMBALERT
pulldown”. Furthermore, “if the host still sees SMBALERT
low when the message transfer is complete, it knows to read
the ARA again”. This SMBus “disengaging of SMBALERT”
requirement prevents locking up the SMBus alert line. Com-
petitive parts may address this “disengaging of SMBALERT”
requirement differently than the LM86 or not at all. SMBus
systems that implement the ARA protocol as suggested for
the LM86 will be fully compatible with all competitive parts.
The LM86 fulfills “disengaging of SMBALERT” by setting the
ALERT mask bit (bit D7 in the Configuration register, at
address 09h) after successfully sending out its address in
response to an ARA and releasing the ALERT output pin.
Once the ALERT mask bit is activated, the ALERT output pin
will be disabled until enabled by software. In order to enable
the ALERT the master must read the STATUS REGISTER,
at address 02h, during the interrupt service routine and then
reset the ALERT mask bit in the Configuration register to 0 at
the end of the interrupt service routine.
The following sequence describes the ARA response proto-
col.
FIGURE 4. ALERT Output as an Interrupt Temperature
Response Diagram
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