LM77CIMX-5/NOPB National Semiconductor, LM77CIMX-5/NOPB Datasheet - Page 9

• Manufacturer Part Number: LM77CIMX-5/NOPB
• Description: IC TEMP SENSOR DIGITAL 8-SOIC
• Manufacturer: National Semiconductor

Specifications of LM77CIMX-5/NOPB

• Function: Temp Monitoring System (Sensor)
• Topology: ADC, Comparator, Register Bank
• Sensor Type: Internal
• Sensing Temperature: -55°C ~ 125°C
• Output Type: I²C™
• Output Alarm: Yes
• Output Fan: No
• Voltage - Supply: 3 V ~ 5.5 V
• Operating Temperature: -55°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (3.9mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: *LM77CIMX-5; *LM77CIMX-5/NOPB; LM77CIMX-5

1.7 FAULT QUEUE
A fault queue of up to 4 faults is provided to prevent false
tripping when the LM77 is used in noisy environments. The 4
faults must occur consecutively to set flags as well as INT and
1.8 INTERNAL REGISTER STRUCTURE
The data registers in the LM77 are selected by the Pointer
register. At power-up the Pointer is set to “00”; the location for
the Temperature Register. The Pointer register latches the
last location it was set to. In Comparator Interrupt Mode, a
read from the LM77 resets the INT output. Placing the device
in Shutdown mode resets the INT and T_CRIT_A outputs. All
registers are read and write, except the Temperature register
which is read only.
A write to the LM77 will always include the address byte and
the Pointer byte. A write to the Configuration register requires
one data byte, while the T
require two data bytes.
Reading the LM77 can take place either of two ways: If the
location latched in the Pointer is correct (most of the time it is
expected that the Pointer will point to the Temperature regis-
ter because it will be the data most frequently read from the
LM77), then the read can simply consist of an address byte,
followed by retrieving the corresponding number of data
bytes. If the Pointer needs to be set, then an address byte,
LOW
, T
HIGH
, and T_CRIT registers
9
T_CRIT_A outputs. The fault queue is enabled by setting bit
4 of the Configuration Register high (see Section 1.11).
pointer byte, repeat start, and another address byte plus re-
quired number of data bytes will accomplish a read.
The first data byte is the most significant byte with most sig-
nificant bit first, permitting only as much data as necessary to
be read to determine the temperature condition. For instance,
if the first four bits of the temperature data indicates a critical
condition, the host processor could immediately take action
to remedy the excessive temperature. At the end of a read,
the LM77 can accept either Acknowledge or No Acknowledge
from the Master (No Acknowledge is typically used as a signal
for the slave that the Master has read its last byte).
An inadvertent 8-bit read from a 16-bit register, with the D7
bit low, can cause the LM77 to stop in a state where the SDA
line is held low as shown in
further bus communication until at least 9 additional clock cy-
cles have occurred. Alternatively, the master can issue clock
cycles until SDA goes high, at which time issuing a “Stop”
condition will reset the LM77.
Figure
4. This can prevent any
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