LM87CIMTX/NOPB National Semiconductor, LM87CIMTX/NOPB Datasheet - Page 7

IC MONITOR SYS HARDWARE 24TSSOP

LM87CIMTX/NOPB

Manufacturer Part Number
LM87CIMTX/NOPB
Description
IC MONITOR SYS HARDWARE 24TSSOP
Manufacturer
National Semiconductor
Series
PowerWise®r
Datasheet

Specifications of LM87CIMTX/NOPB

Function
Hardware Monitor
Topology
ADC (Sigma Delta), Comparator, Fan Speed Control, Register Bank
Sensor Type
External & Internal
Sensing Temperature
-40°C ~ 125°C, External Sensor
Output Type
I²C™/SMBus™
Output Alarm
No
Output Fan
Yes
Voltage - Supply
2.8 V ~ 3.8 V
Operating Temperature
-40°C ~ 125°C
Mounting Type
Surface Mount
Package / Case
24-TSSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
*LM87CIMTX
*LM87CIMTX/NOPB
LM87CIMTX

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
LM87CIMTX/NOPB
Manufacturer:
NS/TI
Quantity:
110
Company:
Part Number:
LM87CIMTX/NOPB
Quantity:
1 180
Company:
Part Number:
LM87CIMTX/NOPB
Quantity:
1 180
An x indicates that the diode exists.
Note 9: Typicals are at T
Note 10: Limits are guaranteed to National's AOQL (Average Outgoing Quality Level).
Note 11: The Temperature Error specification does not include an additional error of ±1°C, caused by the quantization error.
Note 12: The Temperature Error will vary less than ±1°C over the operating Vcc range of 2.8V to 3.8V.
Note 13: TUE (Total Unadjusted Error) includes Offset, Gain and Linearity errors of the ADC.
Note 14: Total Monitoring Cycle Time includes all diode checks, temperature conversions and analog input voltage conversions. Fan tachometer readings are
determined separately and do not affect the completion of the monitoring cycle.
Note 15: This is the lowest DAC code guaranteed to give a non-zero DAC output.
Note 16: The total fan count is based on 2 pulses per revolution of the fan tachometer output.
Note 17: Timing specifications are tested at the specified logic levels, V
ADD/NTEST_OUT
FAN1–FAN2
Pin Name
SMBData
SMBCLK
RESET#
INT#
CI
J
= T
D1
x
x
x
x
x
x
x
A
= 25 °C and represent most likely parametric norm.
D2
x
x
x
x
x
x
x
D3
x
x
x
x
x
x
x
R1
0
0
0
0
0
0
0
FIGURE 2. ESD Protection Input Structure
R2
100k
100k
R3
1M
1M
1M
1M
1M
1M
1M
R4
IL
for a falling edge and V
7
+3.3Vin, +2.5Vin, Vccp1,
DACOut/NTEST_IN
VID4–VID0
Pin Name
THERM
+12Vin
Vccp2
+5Vin
IH
for a rising edge.
10099505
D1
x
x
x
x
x
x
D2
x
x
x
x
x
x
D3
x
x
x
x
R1
0
0
0
R1+R2
R1+R2
R1+R2
130k
130k
130k
R2
www.national.com
100k 1M
100k 1M
R3
1M
1M
R4

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