ADT7473ARQZ-1R7 ON Semiconductor, ADT7473ARQZ-1R7 Datasheet - Page 11

• Manufacturer Part Number: ADT7473ARQZ-1R7
• Description: IC THERM MON FAN CTLR 16-QSOP
• Manufacturer: ON Semiconductor
• Series: dBCool®r

Specifications of ADT7473ARQZ-1R7

• Function: Fan Control, Temp Monitor
• Topology: ADC, Comparator, Fan Speed Counter, Multiplexer, Register Bank
• Sensor Type: External & Internal
• Sensing Temperature: -40°C ~ 125°C, External Sensor
• Output Type: SMBus™
• Output Alarm: No
• Output Fan: Yes
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 16-QSOP
• Full Temp Accuracy: +/- 0.5 C
• Digital Output - Bus Interface: Serial (3-Wire, 4-Wire)
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

without first writing to the address pointer register, if the
address pointer register is already at the correct value.
However, it is not possible to write data to a register without
writing to the address pointer register, because the first data
byte of a write is always written to the address pointer
register.
protocols, the ADT7473/ADT7473−1 also supports the read
byte protocol. (See System Management Bus (SMBus)
Specifications Version 2 for more information; this
document is available from Intel.)
succession, the master can send a repeat start condition
instead of a stop condition to begin a new operation.
Write Operations
various read and write operations. The ADT7473/
ADT7473−1 uses the following SMBus write protocols. The
following abbreviations are used in the diagrams:
S—Start
P—Stop
R—Read
W—Write
A—Acknowledge
A—No Acknowledge
Send Byte
command byte to a slave device, as follows:
It is possible to read a data byte from a data register
In addition to supporting the send byte and receive byte
If several read or write operations must be performed in
The SMBus specification defines several protocols for
In this operation, the master device sends a single
SDA
1. The master device asserts a start condition on
2. The master sends the 7−bit slave address followed
3. The addressed slave device asserts ACK on SDA.
4. The master sends a command code.
5. The slave asserts ACK on SDA.
SCL
SDA
SCL
START BY
START BY
MASTER
SDA.
by the write bit (active low).
MASTER
1
0
1
0
1
1
SERIAL BUS ADDRESS BYTE
SERIAL BUS ADDRESS BYTE
0
0
Figure 19. Reading Data from a Previously Selected Register
Figure 18. Writing to the Address Pointer Register Only
1
FRAME 1
1
FRAME 1
1
1
1
1
0
0
ADT7473/ADT7473−1
ADT7473/ADT7473−1
http://onsemi.com
R/W
R/W
ACK. BY
ACK. BY
9
9
11
D7
D7
1
1
used to write a register address to RAM for a subsequent
single−byte read from the same address. This operation is
illustrated in Figure 20.
immediately after setting up the address, it can assert a repeat
start condition immediately after the final ACK and carry
out a single−byte read without asserting an intermediate stop
condition.
Write Byte
and one data byte to the slave device, as follows:
For the ADT7473/ADT7473−1, the send byte protocol is
If the master is required to read data from the register
In this operation, the master device sends a command byte
The single byte write operation is illustrated in Figure 21.
D6
D6
6. The master asserts a stop condition on SDA and
1. The master device asserts a start condition on SDA.
2. The master sends the 7−bit slave address followed
3. The addressed slave device asserts ACK on SDA.
4. The master sends a command code.
5. The slave asserts ACK on SDA.
6. The master sends a data byte.
7. The slave asserts ACK on SDA.
8. The master asserts a stop condition on SDA, and
Figure 21. Single−Byte Write to a Register
ADDRESS POINTER REGISTER BYTE
the transaction ends.
Figure 20. Setting a Register Address for
by the write bit (active low).
the transaction ends.
D5
D5
S
1
DATA BYTE FROM ADT7473
ADDRESS W A
SLAVE
D4
D4
S
1
2
ADDRESS
FRAME 2
FRAME 2
SLAVE
D3
Subsequent Read
D3
2
3
D2
D2
W A
REGISTER
ADDRESS
3
ADT7473/ADT7473−1
4
D1
D1
REGISTER
ADDRESS
4
D0
D0
5
A
NO ACK. BY
MASTER
ACK. BY
DATA
5 6
A P
6
9
9
A P
7 8
STOP BY
MASTER
STOP BY
MASTER