LM80CIMT-5/NOPB National Semiconductor, LM80CIMT-5/NOPB Datasheet - Page 22

• Manufacturer Part Number: LM80CIMT-5/NOPB
• Description: IC MONITOR SYS HARDWAR 24-TSSOP
• Manufacturer: National Semiconductor
• Series: PowerWise®r

Specifications of LM80CIMT-5/NOPB

• Function: Hardware Monitor
• Topology: ADC, Comparator, Fan Speed Counter, Register Bank
• Sensor Type: External & Internal
• Sensing Temperature: -25°C ~ 125°C, External Sensor
• Output Type: I²C™
• Output Alarm: No
• Output Fan: No
• Voltage - Supply: 2.8 V ~ 5.75 V
• Operating Temperature: -25°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 24-TSSOP
• Manual Reset: Not Resettable
• Watchdog: Watchdog
• Battery Backup Switching: No
• Supply Voltage (max): 5.75 V
• Supply Voltage (min): 2.8 V
• Supply Current (typ): 200 uA (Typ)
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 25 C
• Power Fail Detection: No
• Ic Output Type: Digital
• Sensing Accuracy Range: ± 3°C
• Supply Current: 200µA
• Supply Voltage Range: 2.8V To 5.75V
• Sensor Case Style: TSSOP
• No. Of Pins: 24
• Filter Terminals: Solder
• Rohs Compliant: Yes
• Accuracy %: 3°C
• For Use With: LM80EVAL - EVALUATION BOARD FOR LM80
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: *LM80CIMT-5; *LM80CIMT-5/NOPB; LM80CIMT-5

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Bit
0
1
2
3
4
5
6
7
12.3 Configuration Register—Address 00h
Power on default <7:0> = 00001000 binary
Start
INT Enable
INT polarity select Read/Write A one selects an active high open source output while a zero selects an active low open drain
INT_Clear
RESET
Chassis Clear
GPO
INITIALIZATION
Name
Read/Write A one enables startup of monitoring operations, a zero puts the part in standby mode.
Read/Write A one enables the INT Interrupt output.
Read/Write A one disables the INT and RST_OUT/OS outputs without affecting the contents of Interrupt
Read/Write A one outputs at least a 10 ms active low reset signal at RESET, if <7> = 1 and <6> = 0 in the
Read/Write A one clears the CI (Chassis Intrusion) pin. This bit clears itself after the CI pins cleared.
Read/Write A one in this bit drives a one on GPO (General Purpose Output) pin.
Read/Write A one restores power on default value to the Configuration Register, Interrupt Status Registers,
Read/Write
Note: The outputs of Interrupt pins will not be cleared if the user writes a zero to this location after
an interrupt has occurred unlike “INT_Clear” bit.At start up, limit checking functions and scanning
begin. Note, all limits should be set in the Value RAM before setting this bit HIGH.
output.
Status Registers. The device will stop monitoring. It will resume upon clearing of this bit.
Fan Divisor/RST_OUT/OS Register. This bit is cleared once the pulse has gone inactive.
Interrupt Mask Registers, Fan Divisor/RST_OUT/OSRegister, and the OS Configuration/
Temperature Resolution Register. This bit clears itself since the power on default is zero.
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Description