ADP3162JR-REEL ON Semiconductor, ADP3162JR-REEL Datasheet - Page 10

• Manufacturer Part Number: ADP3162JR-REEL
• Description: IC REG BUCK 5BIT 2PHASE 16-SOIC
• Manufacturer: ON Semiconductor

Specifications of ADP3162JR-REEL

• Rohs Status: RoHS non-compliant
• Applications: Controller, Intel Tualatin
• Voltage - Input: 5V, 12V
• Number Of Outputs: 2
• Voltage - Output: 1.05 ~ 1.83 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 16-SOIC (3.9mm Width)

ADP3162
dictates whether standard threshold or logic-level threshold
MOSFETs must be used. Since V
MOSFETs (V
The maximum output current I
ment for the power MOSFETs. When the ADP3162 is operating
in continuous mode, the simplifying assumption can be made
that in each phase one of the two MOSFETs is always conduct-
ing the average inductor current. For V
1.7 V, the duty ratio of the high-side MOSFET is:
The duty ratio of the low-side (synchronous rectifier) MOSFET is:
The maximum rms current of the high-side MOSFET during
normal operation is:
The maximum rms current of the low-side MOSFET is:
The R
able dissipation. If 10% of the maximum output power is
allowed for MOSFET dissipation, the total dissipation in the
four MOSFETs of the two-phase converter will be:
Allocating half of the total dissipation for the pair of high-side
MOSFETs and half for the pair of low-side MOSFETs, and
assuming that the resistive and switching losses of the high-side
MOSFET are equal, the required maximum MOSFET resis-
tances will be:
An IRL3803 MOSFET from International Rectifier (R
6 mΩ nominal, 9 mΩ worst-case) is a good choice for both the
high-side and low-side. The high-side MOSFET dissipation is:
R
R
DS ON LS MAX
P
DS ON HS MAX
MOSFET TOTAL
(
V
D
D
I
I
28
(
HSF MAX
LSF MAX
DS(ON)
IN
HSF
LSF MAX
2
)
A
)
(
P
×
(
(
(
(
HSF
=
(
I
L PK
0 36
V
for each MOSFET can be derived from the allow-
V
(
.
)
)
2
OUT
)
)
)
=
GS(TH)
IN
=
=
=
=
×
)
= −
)
R
=
P
I
0 1
4
×
I
1
×
I
DS ON HS
HFS MAX
2
.
MOSFET TOTAL
G
=
O
×
P
8
Q



(
1
×
MOSFET TOTAL
1 8
I
G
×
D
< 2.5 V) are strongly recommended.
V
(
5
2
.
+
D
LSF MAX
HSF MAX
OUT
I
×
V
)
2
V
HSF
3 28
HSF MAX
(
f
(
5 8
SW
×
(
)
×
.
(
=
×
×
(
I
×
O
36
I
+
A
)
O



)
2
=
V
)
A
HSF MAX
1
2
D
D
%
determines the R
=
GATE
0 1 1 8
)
=
)
IN
+
2
HSF
LSF
.
4

 =

64
=
(
I
×
×
×
L
8
3
%
2
5 0
(
Q
< 8 V, logic-level threshold
11 3
(
= 11 3
.
×
×
8 5
.
RIPPLE
IN
rr
5 0
)
.
V
( .
I
.
.
W
8 5
×
+
= 12 V and V
O
×
A
.
2
W
A
f
28
SW
)
)
A
A
2

 =

)
A
2
=
DS(ON)
=
9 8
=
5 0
.
8 6
.
.
DS(ON)
m
W
Ω
require-
m
OUT
Ω
=
=
(16)
(17)
(18)
(19)
(20)
(21)
(22)
(23)
where the second term represents the turn-off loss of the
MOSFET and the third term represents the turn-on loss due to
the stored charge in the body diode of the low-side MOSFET.
(In the second term, Q
the gate for turn-off and I
data sheet, for the IRL3803 the value of Q
and the peak gate drive current (I
is about 1 A. In the third term Q
body diode of the low-side MOSFET at the valley of the induc-
tor current. The data sheet of the IRL3803 gives 450 nC for the
stored charge at 71 A. That value corresponds to a stored charge of
80 nC at the valley of the inductor current. In both terms f
the actual switching frequency of the MOSFETs, or 200 kHz.
I
Substituting the above data in Equation 23 and using the worst-
case value for the MOSFET resistance yields a conduction loss
of 0.7 W, a turn-off loss of 1.2 W, and a turn-on loss of 0.08 W.
Thus the worst-case total loss in a high-side MOSFET is 1.98 W.
The worst-case low-side MOSFET dissipation is:
(Note that there are no switching losses in the low-side MOSFET.)
C
In continuous inductor-current mode, the source current of the
high-side MOSFET is approximately a square wave with a duty
ratio equal to V
maximum output current. To prevent large voltage transients, a
low ESR input capacitor sized for the maximum rms current
must be used. The maximum rms capacitor current is given by:
Note that the capacitor manufacturer’s ripple current ratings are
often based on only 2000 hours of life. This makes it advisable
to further derate the capacitor, or to choose a capacitor rated at
a higher temperature than required. Several capacitors may be
placed in parallel to meet size or height requirements in the
design. In this example, the input capacitor bank is formed by
four 1000 µF, 16 V Rubycon capacitors.
The ripple voltage across the three paralleled capacitors is:
To reduce the input-current di/dt to below the recommended
maximum of 0.1 A/µs, an additional small inductor (L > 1 µH
@ 5 A) should be inserted between the converter and the supply
bus. That inductor also acts as a filter between the converter
and the primary power source.
L(PK)
IN
P
LSF
Selection and Input Current di/dt Reduction
I
28
is the peak current in the inductor, or 17.8 A.)
C RMS
28
2
(
V
=
A
2
C RIPPLE
R
A
(
×
DS ON LS
)



=
(
24
2 0 36
I
×
2
OUT
4
O
m
)
)
=
Ω
.
×
/V
2
I
n
+
O
I
×
IN
−
G
2
4 1000
×
D
LSF MAX
(
G
×
is the gate charge to be removed from
and an amplitude of one-half of the



2 0 36
HFS
is the gate turn-off current. From the
ESR
(
×
n
C
−
.
C
(
)
µ
0 36
2
rr
=
F
+
.
G
)
×
is the charge stored in the
2
) provided by the ADP3412
9
n
×
D
C
m
=
200
HFS
Ω
×
6 3
.
D
C
×
kHz
)
IN
HSF
11 3
2
G
A
=
×
is about 140 nC
.

 =

f
SW
A
2
90

 =

=
1 15
mV
.
W
SW
(24)
(25)
(26)
is