NCP5314FTR2 ON Semiconductor, NCP5314FTR2 Datasheet - Page 17

• Manufacturer Part Number: NCP5314FTR2
• Description: IC CTRLR BUCK CPU 2/3/4PH 32LQFP
• Manufacturer: ON Semiconductor

Specifications of NCP5314FTR2

• Applications: Controller, CPU
• Voltage - Input: 9.5 ~ 13.2 V
• Number Of Outputs: 4
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 32-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Voltage - Output: -
• Other names: NCP5314FTR2OSTR

for the lower threshold and VID + 80 mV for the upper
threshold, a simple equation can be provided to assist the
designer in selecting a resistor divider to provide the desired
PWRGD performance.
after a delay period has been passed. A “power bad” event
does not cause PWRGD to go low unless it is sustained
through the delay time of 250 s. If the anomaly disappears
before the end of the delay, the PWRGD output will never
be set low.
advised to connect external resistors as necessary to limit the
current into this pin to 4 mA or less.
PWRGD
Undervoltage Lockout
This circuit keeps the IC’s output drivers low until V
applied to the IC reaches 9 V. The GATE outputs are disabled
when V
Soft−Start
The total SS capacitance will begin to charge with a current
of 40 A. The error amplifier directly charges the COMP
capacitance. An internal clamp ensures that the COMP pin
voltage will always be less than the voltage at the SS pin,
ensuring proper startup behavior. All GATE outputs are held
HIGH
LOW
Since the internally−set thresholds for PWRLS are VID/2
The logic circuitry inside the chip sets PWRGD low only
In order to use the PWRGD pin as specified, the user is
The NCP5314 includes an undervoltage lockout circuit.
At initial power−up, both SS and COMP voltages are zero.
Figure 23. Adjusting the PWRGD Threshold
CC
PWRGD
Figure 22. PWRGD Assertion Window
drops below 8 V.
lo-
w
V LOWER +
V UPPER + V VID ) 80 mV
V
Ç Ç Ç
Ç Ç Ç
Ç Ç Ç
É É É
É É É
OUT
−2.6% +2.6
V
LOWER
%
R1
R2
V VID
2
PWRGD
high
@
PWRLS
R 1 ) R 2
R 1
Ç Ç Ç
Ç Ç Ç
Ç Ç Ç
É É É
É É É
VID + 80 mV
−5.0% +5.0
%
PWRGD
http://onsemi.com
low
V
OUT
CC
NCP5314
17
low until the COMP voltage reaches 0.6 V. Once this
threshold is reached, the GATE outputs are released to
operate normally.
Current Limit
if the voltage between the Current Sense pins (CSxN and
CSxP) exceeds the fixed threshold (Single Pulse Current
Limit), the PWM comparator is turned off. This provides
fast peak current protection for individual phases. Second,
the individual phase currents are summed and externally
low−pass filtered to compare an averaged current signal to
a user adjustable voltage on the I
is exceeded, the fault latch trips and the converter is latched
off. V
Fault Protection Logic
prevent harmful modes of operation from occurring. The
fault logic is described in Table 1.
Gate Outputs
drivers. Accordingly, the gate outputs are capable of driving
a 100 pF load with typical rise and fall times of 5 ns.
Digital to Analog Converter (DAC)
6−bit, 0.5% DAC. The VID pins must be pulled high
externally. A 1.5 k
recommended to meet Intel specifications. To ensure valid
logic signals, the designer should ensure at least 800 mV will
be present at the IC for a logic high.
Characteristics section of the data sheet. These outputs are
consistent with VR10.x and processor specifications. The
DAC output is 20 mV below the VID code specification.
power supply to turn its output off in the event of a 11111X
VID code. When the DAC sees such a code, the GATE pins
stop switching and go low. This condition is described in
Table 1.
Adjusting the Number of Phases
architecture. Designers may choose any number of phases
up to four. The phase delay is automatically adjusted to
match the number of phases that will be used. This feature
allows the designer to select the number of phases required
for a particular application.
a 90 degree delay between pulses. No special connections
are required.
Tie together CS4N and CS4P, and then pull both pins to V
The remaining phases will continue to switch, but now there
Two levels of over−current protection are provided. First,
The NCP5314 includes fault protection circuitry to
The NCP5314 is designed to operate with external gate
The output voltage of the NCP5314 is set by means of a
The output of the DAC is described in the Electrical
The latest VRM and processor specifications require a
The NCP5314 was designed with a selectable−phase
Four−phase operation is standard. All phases switch with
Three−phase operation is achieved by disabling phase 4.
CC
must be recycled to reset the latch.
pullup to a maximum of 3.3 V is
LIM
pin. If the I
LIM
voltage
CC
.