LM20323MH/NOPB National Semiconductor, LM20323MH/NOPB Datasheet - Page 13

IC REG SYNC BUCK 3A ADJ 20TSSOP

LM20323MH/NOPB

Manufacturer Part Number
LM20323MH/NOPB
Description
IC REG SYNC BUCK 3A ADJ 20TSSOP
Manufacturer
National Semiconductor
Series
PowerWise®r
Type
Step-Down (Buck)r
Datasheet

Specifications of LM20323MH/NOPB

Internal Switch(s)
Yes
Synchronous Rectifier
Yes
Number Of Outputs
1
Voltage - Output
0.8 ~ 32 V
Current - Output
3A
Frequency - Switching
520kHz
Voltage - Input
4.5 ~ 36 V
Operating Temperature
-40°C ~ 125°C
Mounting Type
Surface Mount
Package / Case
20-TSSOP Exposed Pad, 20-eTSSOP, 20-HTSSOP
For Use With
LM20323EVAL - EVALUATION BOARD FOR THE LM20323
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Power - Output
-
Other names
LM20323MH
The power stage transfer function is dictated by the modula-
tor, output LC filter, and load; while the feedback transfer
function is set by the feedback resistor ratio, error amp gain
and external compensation network.
To achieve a -20dB/decade slope, the error amplifier zero,
located at f
ter pole (f
Compensation of the LM20323 is achieved by adding an RC
network as shown in Figure 4 below.
A good starting value for C
Once the value of C
approximated using the equation below to cancel the output
filter pole (f
A higher crossover frequency can be obtained, usually at the
expense of phase margin, by lowering the value of C
recalculating the value of R
recalculating R
lower crossover frequency. As with any attempt to compen-
sate the LM20323 the stability of the system should be verified
for desired transient droop and settling time.
For low duty cycle operation, when the on-time of the switch
node is less than 200ns, an additional capacitor (C
be added from the COMP pin to AGND. The recommended
value of this capacitor is 20pF. If low duty cycle jitter on the
switch node is observed, the value of this capacitor can be
increased to improve noise immunity; however, values much
larger than 100pF will cause the pole f
frequency degrading the loop stability.
BOOT CAPACITOR (C
The LM20323 integrates an N-channel buck switch and as-
sociated floating high voltage level shift / gate driver. This gate
driver circuit works in conjunction with an internal diode and
an external bootstrap capacitor. A 0.1 µF ceramic capacitor,
connected with short traces between the BOOT pin and SW
pin, is recommended. During the off-time of the buck switch,
the SW pin voltage is approximately 0V and the bootstrap ca-
pacitor is charged from VCC through the internal bootstrap
diode.
SUB-REGULATOR BYPASS CAPACITOR (C
The capacitor at the VCC pin provides noise filtering for the
internal sub-regulator. The recommended value of C
should be no smaller than 0.1 µF and no greater than 1 µF.
The capacitor should be a good quality ceramic X5R or X7R
capacitor. In general, a 1 µF ceramic capacitor is recom-
FIGURE 4. Compensation Network for LM20323
P(FIL)
Z(EA)
P(FIL)
).
, should be positioned to cancel the output fil-
C1
) as shown in Figure 3.
will provide additional phase margin at a
C1
is chosen the value of R
BOOT
C1
C1
)
for most applications is 2.2 nF.
. Likewise, increasing C
P2(EA)
30051545
to move to a lower
VCC
C1
C2
should be
)
) should
C1
C1
and
and
VCC
13
mended for most applications. The VCC regulator should not
be used for other functions since it isn't protected against
short circuit.
SETTING THE START UP TIME (C
The addition of a capacitor connected from the SS pin to
ground sets the time at which the output voltage will reach the
final regulated value. Larger values for C
start up times. Table 3, shown below provides a list of soft
start capacitors and the corresponding typical start up times.
If different start up times are needed the equation shown be-
low can be used to calculate the start up time.
As shown above, the start up time is influenced by the value
of the soft-start capacitor C
current I
While the soft-start capacitor can be sized to meet many start
up requirements, there are limitations to its size. The soft-start
time can never be faster than 1 ms due to the internal default
1 ms start up time. When the device is enabled there is an
approximate time interval of 50 µs when the soft-start capac-
itor will be discharged just prior to the soft-start ramp. If the
enable pin is rapidly pulsed or the soft-start capacitor is large
there may not be enough time for C
resulting in start up times less than predicted. To aid in dis-
charging of soft-start capacitor during long disable periods an
external 1MΩ resistor from SS/TRK to ground can be used
without greatly affecting the start up time.
USING PRECISION ENABLE AND POWER GOOD
The precision enable (EN) and power good (PGOOD) pins of
the LM20323 can be used to address many sequencing re-
quirements. The turn-on of the LM20323 can be controlled
with the precision enable pin by using two external resistors
as shown in Figure 5 .
FIGURE 5. Sequencing LM20323 with Precision Enable
TABLE 3. Start Up Times for Different Soft-Start
Start Up Time (ms)
SS
.
10
15
20
1
5
Capacitors
SS
and the 4.5 µA soft-start pin
SS
SS
to completely discharge
)
SS
C
will result in longer
SS
none
100
120
33
68
(nF)
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30051562

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