KSZ8695PX Micrel Inc, KSZ8695PX Datasheet - Page 16

• Manufacturer Part Number: KSZ8695PX
• Description: IC SWITCH 10/100 1PORT 289PBGA
• Manufacturer: Micrel Inc

Specifications of KSZ8695PX

• Applications: *
• Mounting Type: Surface Mount
• Package / Case: 289-PBGA
• Operating Supply Voltage (typ): 1.8V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 289
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: KSZ8695PX-EVAL - EVAL KIT EXPERIMENT ONLY KSZ8695
• Lead Free Status / RoHS Status: Compliant, Lead free / RoHS Compliant
• Other names: 576-1024

KS8695PX
M9999-091605
Switch Engine (continued)
• Supports 802.1Q tag-based VLAN and port-based VLAN
• Supports 8.2,1p-based priority, DiffServ priority, and post-based priority
• Integrated address look-up engine, supports 1K absolute MAC addresses
• Automatic address learning, address aging, and address migration
• Broadcast storm protection
• Full-duplex IEEE 802.3x fl ow control
• Half-duplex back pressure fl ow control
• Supports IGMP snooping
• Spanning Tree Protocol support
Advanced Memory Controller Features
• Supports glueless connection to two banks of ROM/SRAM/FLASH memory with programmable 8/16/32 bit data bus
• Supports glueless connection to two SDRAM banks with programmable 8/16/32-bit data bus and programmable
• Supports three external I/O banks with programmable 8/16/32-bit data bus and programmable access timing
• Programmable system clock speed for power management
• Automatic address line mapping for 8/16/32-bit accesses on Flash, ROM, SRAM, and SDRAM interfaces
Direct Memory Access (DMA) Engines
• Independent MAC DMA engine with programmable burst mode for WAN port
• Independent MAC DMA engine with programmable burst mode for LAN ports
• Supports little-endian byte ordering for memory buffers and descriptors
• Contains large independent receive and transmit FIFOs (3KB receive/3KB transmit) for back-to-back packet receive,
• Data alignment logic and scatter gather capability
Protocol Engine/XceleRouter Technology
• Supports IPv4 IP header/TCP/UDP packet checksum generation for host CPU offl oading
• Supports IPv4 packet fi ltering based on checksum errors
Network Interface
• Features fi ve MAC units and fi ve PHY units
• Supports 10BASE-T and 100BASE-TX on all LAN ports and one WAN port. Also supports 100BASE-FX on the WAN
• Supports automatic CRC generation and checking
• Supports automatic error packet discard
• Supports IEEE 802.3 auto-negotiation algorithm of full-duplex and half-duplex operation for 10Mbps and 100Mbps
• Supports full-/half-duplex operation on PHY interfaces
• Fully compliant with IEEE 802.3 Ethernet standards
• IEEE 802.3 full-duplex fl ow control and half-duplex backpressure collision fl ow control
• Supports MDI/MDI-X auto-crossover
Peripherals
• Twenty-eight interrupt sources, including four external interrupt sources
• Normal or fast interrupt mode (IRQ, FIQ) supported
• Prioritized interrupt handling
• Sixteen programmable general purpose I/O. Pins individually confi gurable to input, output, or I/O mode for dedicated
• Two programmable 32-bit timers with watchdog timer capability
• High-speed UART interface up to 115kbps
Other Features
• Integrated PLL to generate CPU and system clocks
• JTAG development interface for ICE connection
• 19mm x 19mm 289-pin PBGA
• 1.8V CMOS for core and 3.3V for I/O
and programmable access timing
RAS/CAS latency
and guaranteed no under-run packet transmit
port and on one LAN port
signals.
16
September 2005
Micrel