KSZ8695PX Micrel Inc, KSZ8695PX Datasheet - Page 26

• Manufacturer Part Number: KSZ8695PX
• Description: IC SWITCH 10/100 1PORT 289PBGA
• Manufacturer: Micrel Inc

Specifications of KSZ8695PX

• Applications: *
• Mounting Type: Surface Mount
• Package / Case: 289-PBGA
• Operating Supply Voltage (typ): 1.8V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 289
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: KSZ8695PX-EVAL - EVAL KIT EXPERIMENT ONLY KSZ8695
• Lead Free Status / RoHS Status: Compliant, Lead free / RoHS Compliant
• Other names: 576-1024

Note:
1. I = Input.
General Purpose I/O Pins (continued)
September 2005
KS8695PX
O = Output.
I/O = Bidirectional.
D12
D12
D12
D12
D12
B12
B12
B12
B12
B12
C12
C12
C12
C12
C12
A12
A12
A12
A12
A12
D13
D13
D13
D13
D13
B13
B13
B13
B13
B13
C13
C13
C13
C13
C13
A13
A13
A13
A13
A13
B14
B14
B14
B14
B14
C14
C14
C14
C14
C14
A14
A14
A14
A14
A14
D15
D15
D15
D15
D15
B15
B15
B15
Pin
Pin
Pin
D4
D4
D4
D4
D4
C2
C2
C2
C2
C2
C3
C3
C3
C3
C3
C4
C4
C4
C4
C4
B2
B2
B2
B2
B2
B3
B3
B3
B3
B3
B4
B4
B4
B4
B4
A4
A4
A4
A4
A4
D5
D5
D5
D5
D5
B5
B5
B5
B5
B5
C5
C5
C5
C5
C5
A5
A5
A5
A5
A5
D6
D6
D6
D6
D6
B6
B6
B6
B6
B6
C6
C6
C6
C6
C6
B7
B7
B7
B7
B7
C7
C7
C7
C7
C7
A7
A7
A7
A7
A7
D8
D8
D8
D8
D8
B8
B8
B8
B8
B8
D9
D9
D9
D9
D9
A8
A8
A8
A8
A8
C9
C9
C9
C9
C9
GNT1N
GNT1N
GNT1N
GNT1N
GNT1N
REQ1N
REQ1N
REQ1N
REQ1N
REQ1N
PAD31
PAD31
PAD31
PAD31
PAD31
PAD30
PAD30
PAD30
PAD30
PAD30
PAD29
PAD29
PAD29
PAD29
PAD29
PAD28
PAD28
PAD28
PAD28
PAD28
PAD27
PAD27
PAD27
PAD27
PAD27
PAD26
PAD26
PAD26
PAD26
PAD26
PAD25
PAD25
PAD25
PAD25
PAD25
PAD24
PAD24
PAD24
PAD24
PAD24
PAD23
PAD23
PAD23
PAD23
PAD23
PAD22
PAD22
PAD22
PAD22
PAD22
PAD21
PAD21
PAD21
PAD21
PAD21
PAD20
PAD20
PAD20
PAD20
PAD20
PAD19
PAD19
PAD19
PAD19
PAD19
PAD18
PAD18
PAD18
PAD18
PAD18
PAD17
PAD17
PAD17
PAD17
PAD17
PAD16
PAD16
PAD16
PAD16
PAD16
PAD15
PAD15
PAD15
PAD15
PAD15
PAD14
PAD14
PAD14
PAD14
PAD14
PAD13
PAD13
PAD13
PAD13
PAD13
PAD12
PAD12
PAD12
PAD12
PAD12
PAD11
PAD11
PAD11
PAD11
PAD11
PAD10
PAD10
PAD10
PAD10
PAD10
Name
Name
Name
PCLK
PCLK
PCLK
PCLK
PCLK
PAD9
PAD9
PAD9
PAD9
PAD9
PAD8
PAD8
PAD8
PAD8
PAD8
PAD7
PAD7
PAD7
PAD7
PAD7
PAD6
PAD6
PAD6
PAD6
PAD6
PAD5
PAD5
PAD5
PAD5
PAD5
PAD4
PAD4
PAD4
PAD4
PAD4
PAD3
PAD3
PAD3
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
I/O Type
I/O Type
I/O Type
I/O
I/O
I/O
I/O
I/O
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
O
O
O
O
O
I
I
I
I
I
I
I
I
I
I
(1)
Description
Description
PCI bus clock.This signal provides the timing for the PCI bus transactions. This signal
PCI bus clock.This signal provides the timing for the PCI bus transactions. This signal
PCI bus clock.This signal provides the timing for the PCI bus transactions. This signal
PCI bus clock.This signal provides the timing for the PCI bus transactions. This signal
PCI bus clock.This signal provides the timing for the PCI bus transactions. This signal
is used to drive the PCI bus interface and the internal PCI logic. All PCI bus signals
is used to drive the PCI bus interface and the internal PCI logic. All PCI bus signals
is used to drive the PCI bus interface and the internal PCI logic. All PCI bus signals
is used to drive the PCI bus interface and the internal PCI logic. All PCI bus signals
is used to drive the PCI bus interface and the internal PCI logic. All PCI bus signals
are sampled on the rising edges of the PCLK. PCLK can operate from 20MHz to
are sampled on the rising edges of the PCLK. PCLK can operate from 20MHz to
are sampled on the rising edges of the PCLK. PCLK can operate from 20MHz to
are sampled on the rising edges of the PCLK. PCLK can operate from 20MHz to
are sampled on the rising edges of the PCLK. PCLK can operate from 20MHz to
33MHz. For host mode, use PCLKOUT0 signal to drive this input. In guest mode,
33MHz. For host mode, use PCLKOUT0 signal to drive this input. In guest mode,
33MHz. For host mode, use PCLKOUT0 signal to drive this input. In guest mode,
33MHz. For host mode, use PCLKOUT0 signal to drive this input. In guest mode,
33MHz. For host mode, use PCLKOUT0 signal to drive this input. In guest mode,
use the system PCI clock to drive this input.
use the system PCI clock to drive this input.
use the system PCI clock to drive this input.
use the system PCI clock to drive this input.
use the system PCI clock to drive this input.
No Connect
No Connect
No Connect
No Connect
No Connect
No Connect
No Connect
No Connect
No Connect
No Connect
PCI bus grant 1. Active low. In host bridge mode, this is an output signal from the
PCI bus grant 1. Active low. In host bridge mode, this is an output signal from the
PCI bus grant 1. Active low. In host bridge mode, this is an output signal from the
PCI bus grant 1. Active low. In host bridge mode, this is an output signal from the
PCI bus grant 1. Active low. In host bridge mode, this is an output signal from the
internal PCI arbiter to grant PCI bus access to the device connected to REQ1N. In
internal PCI arbiter to grant PCI bus access to the device connected to REQ1N. In
internal PCI arbiter to grant PCI bus access to the device connected to REQ1N. In
internal PCI arbiter to grant PCI bus access to the device connected to REQ1N. In
internal PCI arbiter to grant PCI bus access to the device connected to REQ1N. In
guest bridge mode, this signal is an output to indicate that the KS8695PX is
guest bridge mode, this signal is an output to indicate that the KS8695PX is
guest bridge mode, this signal is an output to indicate that the KS8695PX is
guest bridge mode, this signal is an output to indicate that the KS8695PX is
guest bridge mode, this signal is an output to indicate that the KS8695PX is
requesting to access the PCI bus as a PCI master. In guest bridge mode, this is
requesting to access the PCI bus as a PCI master. In guest bridge mode, this is
requesting to access the PCI bus as a PCI master. In guest bridge mode, this is
requesting to access the PCI bus as a PCI master. In guest bridge mode, this is
requesting to access the PCI bus as a PCI master. In guest bridge mode, this is
basically the KS8695PX’s request output.
basically the KS8695PX’s request output.
basically the KS8695PX’s request output.
basically the KS8695PX’s request output.
basically the KS8695PX’s request output.
No Connect
No Connect
No Connect
No Connect
No Connect
No Connect
No Connect
No Connect
No Connect
No Connect
PCI bus request 1. Active low. In host bridge mode, this is an input signal from the
PCI bus request 1. Active low. In host bridge mode, this is an input signal from the
PCI bus request 1. Active low. In host bridge mode, this is an input signal from the
PCI bus request 1. Active low. In host bridge mode, this is an input signal from the
PCI bus request 1. Active low. In host bridge mode, this is an input signal from the
external PCI device to request PCI bus access. In guest bridge mode, this is an input
external PCI device to request PCI bus access. In guest bridge mode, this is an input
external PCI device to request PCI bus access. In guest bridge mode, this is an input
external PCI device to request PCI bus access. In guest bridge mode, this is an input
external PCI device to request PCI bus access. In guest bridge mode, this is an input
signal from an external PCI bus arbiter granting access to the bus. In guest bridge,
signal from an external PCI bus arbiter granting access to the bus. In guest bridge,
signal from an external PCI bus arbiter granting access to the bus. In guest bridge,
signal from an external PCI bus arbiter granting access to the bus. In guest bridge,
signal from an external PCI bus arbiter granting access to the bus. In guest bridge,
this is basically the KS8695PX's grant input.
this is basically the KS8695PX's grant input.
this is basically the KS8695PX's grant input.
this is basically the KS8695PX's grant input.
this is basically the KS8695PX's grant input.
32-Bit PCI address and data. PCI bus transactions consist of an address
32-Bit PCI address and data. PCI bus transactions consist of an address
32-Bit PCI address and data. PCI bus transactions consist of an address
32-Bit PCI address and data. PCI bus transactions consist of an address
32-Bit PCI address and data. PCI bus transactions consist of an address
phase followed by one or more data phases. Address and data signals are multi-
phase followed by one or more data phases. Address and data signals are multi-
phase followed by one or more data phases. Address and data signals are multi-
phase followed by one or more data phases. Address and data signals are multi-
phase followed by one or more data phases. Address and data signals are multi-
plexed on the same pins. For a PCI write transaction, the source of the data is the
plexed on the same pins. For a PCI write transaction, the source of the data is the
plexed on the same pins. For a PCI write transaction, the source of the data is the
plexed on the same pins. For a PCI write transaction, the source of the data is the
plexed on the same pins. For a PCI write transaction, the source of the data is the
KS8695PX. For a PCI read transaction, the data source is the target. The
KS8695PX. For a PCI read transaction, the data source is the target. The
KS8695PX. For a PCI read transaction, the data source is the target. The
KS8695PX. For a PCI read transaction, the data source is the target. The
KS8695PX. For a PCI read transaction, the data source is the target. The
KS8695PX supports both read and write burst transactions. In the case of a read
KS8695PX supports both read and write burst transactions. In the case of a read
KS8695PX supports both read and write burst transactions. In the case of a read
KS8695PX supports both read and write burst transactions. In the case of a read
KS8695PX supports both read and write burst transactions. In the case of a read
transaction, a special data turn around cycle is needed between the address phase
transaction, a special data turn around cycle is needed between the address phase
transaction, a special data turn around cycle is needed between the address phase
transaction, a special data turn around cycle is needed between the address phase
transaction, a special data turn around cycle is needed between the address phase
and the data phase(s).
and the data phase(s).
and the data phase(s).
and the data phase(s).
and the data phase(s).
26
M9999-091605
Micrel