KSZ8695PX Micrel Inc, KSZ8695PX Datasheet - Page 18

• Manufacturer Part Number: KSZ8695PX
• Description: IC SWITCH 10/100 1PORT 289PBGA
• Manufacturer: Micrel Inc

Specifications of KSZ8695PX

• Applications: *
• Mounting Type: Surface Mount
• Package / Case: 289-PBGA
• Operating Supply Voltage (typ): 1.8V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 289
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: KSZ8695PX-EVAL - EVAL KIT EXPERIMENT ONLY KSZ8695
• Lead Free Status / RoHS Status: Compliant, Lead free / RoHS Compliant
• Other names: 576-1024

KS8695PX
Following pins have second function as factory test of chip
Reset
The KS8695PX has a single reset input that can be driven by a system reset circuit or a simple power on reset circuit. The
KS8695PX also features a reset output (WRSTO) that can be used to reset other devices in the system. WRSTO can be
confi gured as either an active high reset or an active low reset through a strap-in option on pin U17, as shown in Table 1. The
KS8695PX also has a built in watchdog timer. When the watchdog timer is programmed and the timer setting expires, the
KS8695PX resets itself and also asserts WRSTO to reset the other devices in the system. Figure 4 shows a typical system
using the KS8695PX WRSTO as the system reset.
Reset Circuit Diagram
At power-on-reset, R, C,and D1 provide the necessary ramp rise time to reset the Micrel device. The reset out from CPU/
FPGA provides warm reset after power up
M9999-091605
Confi guration
Chip Test Enable
push button
Manual
switch
Power On Reset Circuit
C
Figure 5. Recommended circuit for Interfacing with CPU/FPGA Reset
R
V
CC
Pin Name
TESTEN
ERWEN0/TESTACK
ERWEN1/TESTREQB
ERWEN2/TESTREQA
ERWEN3/TICTESTTENN
UCTSN/BISTEN
UDCDN/SCANEN
URIN/TSTRST
TEST1
TEST2
KS8695PX
D1
Figure 4. Example of a Reset Circuit
RST
Table 2. Confi guration Pins
A17
D1
RESETN
10µF
VCC
KS8695PX
C
18
R
10k
WRSTPLS
EROEN/
WRSTO
D2
Pin #
F17
M17
N17
P17
R17
M14
L15
L14
M4
F4
RST_OUT_n
U17
T17
CPU/FPGA
System Reset
R
V
CC
Setting
‘0’ = normal operation
‘1’ = factory reserved. Used for
factory test of chip and affects all
signals listed in this table.
Set WRSTO to
Active Low
To System
To Memory
September 2005
Micrel