TLE8263-2E Infineon Technologies, TLE8263-2E Datasheet - Page 9

• Manufacturer Part Number: TLE8263-2E
• Description: IC SYSTEM BASIS CHIP DSO-36
• Manufacturer: Infineon Technologies
• Type: Transceiverr

Specifications of TLE8263-2E

• Applications: Automotive
• Mounting Type: Surface Mount
• Package / Case: DSO-36
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: SP000379937

LIN Transceivers
Top performances for low-cost networking
allowing a basic local network connection between the CAN
backbone and actuators, sensors or switches has tremendous-
ly reduced the design efforts and costs. It is thus used in a
fast-growing range of body and convenience applications. As
an active member of the LIN consortium Physical Layer and
Conformance Tests working groups, Infineon has adapted its
portfolio to the latest applications and norms.
TLE6258-2G – a standard k-Line (ISO9141) and LIN transceiver
a broad range of designs:
TLE7259-2G – the enhanced Infineon LIN transceiver
with an inhibit output pin to control the voltage regulator,
mastering the whole node supply for an optimized overall
consumption. The TLE7259-2G is a leading product combining
outstanding benefits:
Compatible to the LIN norms LIN 1.3, 2.1
Bus wake-up capability with low power mode (standby)
Bus short to ground and battery protection
T h E T L E 7 2 5 9 - 2 G offers a sleep mode in conjunction
Excellent EMC coupled to a strong ESD robustness
Very low quiescent current and
bus leakage current in sleep mode
Compatibility to 3.3 V and 5 V logic
Specific LIN 1.3, 2.1 version: TLE7259-2GE
L O C A L I N T E r C O N N E C T N E T W O r k (LIN) bus by
T h E T L E 6 2 5 8 - 2 G is a cost-optimized solution suiting
Specific SAE J 2602 version: TLE7259-2Gu
TLE7269G – the first ever Twin-LIN device
TLE7259-2 in a SO14 package, which gives additional benefits:
Pin out TLE7269G
T h E T L E 7 2 6 9 G offers two LIN transceiver cells type
Smaller overall board area
Integrated pull-up resistors to Vcc for logic pins
reduced total quiescent current
Layout single / twinLIN scalability
rxD2
rxD1
TxD2
TxD1
Wk
Vio
EN
6
2
3
4
5
7
1
(P-DSO-14)
TLE7269G
14
12
10
13
11
9
8
INh1
V
BuS1
GND
BuS2
W2O
INh2
S
TLE7259G
9