ADMC200AP Analog Devices Inc, ADMC200AP Datasheet - Page 11

• Manufacturer Part Number: ADMC200AP
• Description: IC MOTION CO-PROC 12.5MHZ 68PLCC
• Manufacturer: Analog Devices Inc

Specifications of ADMC200AP

• Rohs Status: RoHS non-compliant
• Applications: *
• Mounting Type: Surface Mount
• Package / Case: 68-PLCC

REV. B
DESCRIPTION OF THE REGISTERS
All unspecified register locations are reserved.
SYSCTRL
SYSSTAT
ADCU
ADCV
ADCW
ADCAUX
PWMTM
PWMCHA
PWMCHB
PWMCHC
PWMDT
PWMPD
ID/IQ
PHV1/2/3
PHIP1/2/3
IX/IY
VX, VY
RHOP
RHO
Name
ID/PHV1/VX
IQ/PHV2
IX/PHV3
IY/VY
ADCV
ADCW
ADCAUX
ADCU
SYSCTRL
SYSSTAT
(Clarke and Park).
transformation that are the inputs to the reverse
Park rotation.
tor transformation. Writing to the RHOP regis-
ter causes the forward rotation to start based on
values in RHOP, VD and VQ registers.
transformation. Writing to this register starts
the reverse rotation using the values in the
RHO, PHIP1/2/3 registers.
These are the results of the reverse rotation
(torque and flux components).
These are the results from the forward
Clarke Transformation.
The inputs for reverse vector transformation
These registers contain the results of the Clarke
VX , VY contain the results of the forward
Park rotation.
RHOP is the angle used during the forward vec-
RHO is the angle used during the reverse vector
RHO and RHOP are unsigned ratios of 360 .
For example, 45 degrees would be 45/360
System Control Register (See Table V and VI)
System Status Register (See Table VII)
These registers contain the results from the first
three analog input channels U, V, and W. The
output data format is twos complement and
therefore Bit 0 is always zero as the A/D
converter has 11-bit resolution.
This register contains the conversion result
of the auxiliary channel.
PWM Master Switching Period
PWM Channel A on-time
PWM Channel B on-time
PWM Channel C on-time
PWM Programmable Deadtime Value
PWM Programmable Pulse Deletion Value
A
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
3
A
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
2
Table IV. Read Registers
A
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1
2
12
A
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
.
–11–
Bit 0, 1 Reserved for future use. Always write 0 to these bits.
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Bit
Register Function
Reverse Rotation Result (I
Reverse Rotation Result (I
Reverse Clarke Cos + 0 /Forward Result Cos +240
Reverse Clarke Cos +90 /Forward Cos +90
Reserved
A/D Conversion Result Channel V
A/D Conversion Result Channel W
A/D Conversion Result Auxiliary Channel
A/D Conversion Result Channel U
Reserved
Reserved
Reserved
Reserved
System Control
System Status
Reserved
0
1
3
4
5
6
7
8
10
Function
Reserved, Must Be 0
Reserved, Must Be 0
Enables U Channel Conversion
(1 = Enable) Three/Three-Phase Mode
Enables AUX Channel Conversion
(0 = Disable, 1 = Enable)
Divide External Clock by 2
(0 = No, 1 = Yes)
Park Interrupt Enable
ADC Interrupt Enable
(0 = Disable, 1 = Enable)
IRQ Pin Format (Edge or Level Based
Interrupt Requests) (0 = Edge)
Reverse Rotation (0 = 2/3, 1 = 3/3)
Forward Rotation (1 = Enable)
Table V. System Control (SYSCTRL) Registers
ADC Interrupt Enable. This bit allows interrupts to
be generated via the IRQ pin when the analog-to-
digital conversion process is complete.
Channel U Conversion Enable. If Bit 3 is set to 1, then
Channel U will be converted along with V, W and/or
AUX. This bit selects three-/three-phase mode.
Aux Channel Conversion Enable. If Bit 4 is set to
1, then the AUX input will be converted along with
the channels V, W and/or U.
If Bit 5 = 1, then the external clock will be divided by
two to derive the system clock. If the external clock
frequency is greater than 12.5 MHz, then this bit must
be set.
Park Interrupt Enable. This bit allows interrupts to
be generated when the Park rotation is completed.
DS
QS
)/Forward Cos +120
)/Forward Result Cos +0
ADMC200
RESET
Default
0
0
0
0
0
0
0
0
0