MT9LSDT1672AY-133G3 Micron Technology Inc, MT9LSDT1672AY-133G3 Datasheet - Page 10

• Manufacturer Part Number: MT9LSDT1672AY-133G3
• Description: MODULE SDRAM 128MB 168-DIMM
• Manufacturer: Micron Technology Inc

Specifications of MT9LSDT1672AY-133G3

• Memory Type: SDRAM
• Memory Size: 128MB
• Speed: 133MHz
• Package / Case: 168-DIMM
• Main Category: DRAM Module
• Sub-category: SDRAM
• Module Type: 168UDIMM
• Device Core Size: 72b
• Organization: 16Mx72
• Total Density: 128MByte
• Chip Density: 128Mb
• Access Time (max): 6/5.4ns
• Maximum Clock Rate: 133MHz
• Operating Supply Voltage (typ): 3.3V
• Operating Current: 1.35A
• Number Of Elements: 9
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Operating Temp Range: 0C to 65C
• Operating Temperature Classification: Commercial
• Pin Count: 168
• Mounting: Socket
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 7:
NOTE:
09005aef807b3709
SD9_18C16_32x72AG.fm - Rev. E 6/04 EN
1. For full-page accesses: y = 1,024
2. For a burst length of two, A1–A9 select the block of two
3. For a burst length of four, A2–A9 select the block of
4. For a burst length of eight, A3–A9 select the block of
5. For a full-page burst, the full row is selected and A0–A9
6. Whenever a boundary of the block is reached within a
7. For a burst length of one, A0–A9 select the unique col-
Full Page
LENGTH
BURST
burst; A0 selects the starting column within the block.
four burst; A0-A1 select the starting column within the
block.
eight burst; A0–A2 select the starting column within the
block.
select the starting column.
given sequence above, the following access wraps
within the block.
umn to be accessed, and Mode Register bit M3 is
ignored.For a full-page burst, the full row is selected
and A0–A8 select the starting column.
(y)
2
4
8
A2 A1 A0
(location 0-y)
0
0
0
0
1
1
1
1
STARTING
ADDRESS
COLUMN
n= A0-A9
A1 A0
Burst Definition Table
0
0
1
1
0
0
1
1
0
0
1
1
A0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Cn, Cn+1, Cn+2
0-1-2-3-4-5-6-7
1-2-3-4-5-6-7-0
2-3-4-5-6-7-0-1
3-4-5-6-7-0-1-2
4-5-6-7-0-1-2-3
5-6-7-0-1-2-3-4
6-7-0-1-2-3-4-5
7-0-1-2-3-4-5-6
ORDER OF ACCESSES WITHIN
SEQUENTIAL
Cn+3, Cn+4...
...Cn-1, Cn...
TYPE =
0-1-2-3
1-2-3-0
2-3-0-1
3-0-1-2
0-1
1-0
A BURST
INTERLEAVED
Not Supported
0-1-2-3-4-5-6-7
1-0-3-2-5-4-7-6
2-3-0-1-6-7-4-5
3-2-1-0-7-6-5-4
4-5-6-7-0-1-2-3
5-4-7-6-1-0-3-2
6-7-4-5-2-3-0-1
7-6-5-4-3-2-1-0
128MB (x72, ECC, SR), 256MB (x72, ECC, DR)
TYPE =
0-1-2-3
1-0-3-2
2-3-0-1
3-2-1-0
0-1
1-0
10
CAS Latency
between the registration of a READ command and the
availability of the first piece of output data. The latency
can be set to two or three clocks.
and the latency is m clocks, the data will be available
by clock edge n + m. The DQ will start driving as a
result of the clock edge one cycle earlier (n + m - 1),
and provided that the relevant access times are met,
the data will be valid by clock edge n + m. For example,
assuming that the clock cycle time is such that all rele-
vant access times are met, if a READ command is regis-
tered at T0 and the latency is programmed to two
clocks, the DQ will start driving after T1 and the data
will be valid by T2, as shown in Figure 6, CAS Latency
Diagram. Table 8, CAS Latency Table, indicates the
operating frequencies at which each CAS latency set-
ting can be used.
operation or incompatibility with future versions may
result.
Operating Mode
M7 and M8 to zero; the other combinations of values
for M7 and M8 are reserved for future use and/or test
modes. The programmed burst length applies to both
READ and WRITE bursts.
COMMAND
COMMAND
The CAS latency is the delay, in clock cycles,
If a READ command is registered at clock edge n,
Reserved states should not be used as unknown
The normal operating mode is selected by setting
CLK
CLK
DQ
DQ
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Figure 6: CAS Latency Diagram
READ
READ
T0
T0
168-PIN SDRAM UDIMM
CAS Latency = 2
NOP
NOP
T1
T1
t
t AC
LZ
CAS Latency = 3
T2
NOP
T2
NOP
t
t AC
D
LZ
t OH
OUT
©2004 Micron Technology, Inc.
T3
T3
NOP
D
t OH
OUT
DON’T CARE
UNDEFINED
T4