MT18VDVF12872DG-335F4 Micron Technology Inc, MT18VDVF12872DG-335F4 Datasheet - Page 14

• Manufacturer Part Number: MT18VDVF12872DG-335F4
• Description: MODULE DDR 1GB 184DIMM VLP
• Manufacturer: Micron Technology Inc

Specifications of MT18VDVF12872DG-335F4

• Memory Type: DDR SDRAM
• Memory Size: 1GB
• Speed: 333MT/s
• Package / Case: 184-DIMM
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Figure 5:
Operating Mode
Extended Mode Register
PDF: 09005aef81c73825/Source: 09005aef81c73837
DVF18C64_128x72D_2.fm - Rev. A 8/05 EN
CAS Latency Diagram
The normal operating mode is selected by issuing a MODE REGISTER SET command
with bits A7–A12 each set to zero, and bits A0–A6 set to the desired values. A DLL reset is
initiated by issuing a MODE REGISTER SET command with bits A7 and A9–A12 each set
to zero, bit A8 set to one, and bits A0–A6 set to the desired values. Although not required
by the Micron device, JEDEC specifications recommend when a LOAD MODE REGISTER
command is issued to reset the DLL, it should always be followed by a LOAD MODE
REGISTER command to select normal operating mode.
All other combinations of values for A7–A12 are reserved for future use and/or test
modes. Test modes and reserved states should not be used because unknown operation
or incompatibility with future versions may result.
The extended mode register controls functions beyond those controlled by the mode
register; these additional functions are DLL enable/disable and output drive strength.
These functions are controlled via the bits shown in Figure 6, "Extended Mode Register
Definition Diagram," on page 15. The extended mode register is programmed via the
LOAD MODE REGISTER command to the mode register (with BA0 = 1 and BA1 = 0) and
will retain the stored information until it is programmed again or the device loses power.
The enabling of the DLL should always be followed by a LOAD MODE REGISTER com-
mand to the mode register (BA0/BA1 both LOW) to reset the DLL.
The extended mode register must be loaded when all device banks are idle and no bursts
are in progress, and the controller must wait the specified time before initiating any sub-
sequent operation. Violating either of these requirements could result in unspecified
operation.
COMMAND
COMMAND
DQS
DQS
CK#
CK#
DQ
DQ
CK
CK
READ
READ
Burst Length = 4 in the cases shown
Shown with nominal t AC, t DQSCK, and t DQSQ
T0
T0
CL = 2
TRANSITIONING DATA
CL = 2.5
NOP
NOP
T1
T1
512MB, 1GB: (x72, DR) 184-Pin DDR VLP RDIMM
14
T2
NOP
NOP
T2
Micron Technology, Inc., reserves the right to change products or specifications without notice.
T2n
T2n
DON’T CARE
T3
NOP
NOP
T3
T3n
T3n
Extended Mode Register
©2003, 2004, 2005 Micron Technology, Inc. All rights reserved.