MT8VDDT6464AG-40BF3 Micron Technology Inc, MT8VDDT6464AG-40BF3 Datasheet - Page 11

• Manufacturer Part Number: MT8VDDT6464AG-40BF3
• Description: MODULE DDR SDRAM 512MB 184-DIMM
• Manufacturer: Micron Technology Inc

Specifications of MT8VDDT6464AG-40BF3

• Memory Type: DDR SDRAM
• Memory Size: 512MB
• Speed: 400MT/s
• Package / Case: 184-DIMM
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

General Description
Serial Presence-Detect Operation
Table 5:
PDF: 09005aef80a43556, Source: 09005aef80a43534
DDA8C16_32_64x64AG_2.fm - Rev. E 4/06 EN
CAS Latency (CL) Table
The MT8VDDT1664A, MT8VDDT3264A, and MT8VDDT6464A are high-speed CMOS,
dynamic random-access, 128MB, 256MB, and 512MB memory modules organized in a
x64 configuration. DDR SDRAM modules use internally configured quad-bank DDR
SDRAM devices.
DDR SDRAM modules use a double data rate architecture to achieve high-speed opera-
tion. The double data rate architecture is essentially a 2n-prefetch architecture with an
interface designed to transfer two data words per clock cycle at the I/O pins. A single
read or write access for the DDR SDRAM module effectively consists of a single 2n-bit
wide, one-clock-cycle data transfer at the internal DRAM core and two corresponding n-
bit wide, one-half-clock-cycle data transfers at the I/O pins.
A bidirectional data strobe (DQS) is transmitted externally, along with data, for use in
data capture at the receiver. DQS is an intermittent strobe transmitted by the DDR
SDRAM during READs and by the memory controller during WRITEs. DQS is edge-
aligned with data for READs and center-aligned with data for WRITEs.
DDR SDRAM modules operate from multiple differential clocks (CK and CK#); the
crossing of CK going HIGH and CK# going LOW will be referred to as the positive edge of
CK. Commands (address and control signals) are registered at every positive edge of CK.
Input data is registered on both edges of DQS, and output data is referenced to both
edges of DQS, as well as to both edges of CK.
DDR SDRAM modules incorporate serial presence-detect (SPD). The SPD function is
implemented using a 2,048-bit EEPROM. This nonvolatile storage device contains 256
bytes. The first 128 bytes can be programmed by Micron to identify the module type and
various SDRAM organizations and timing parameters. The remaining 128 bytes of
storage are available for use by the customer. System READ/WRITE operations between
the master (system logic) and the slave EEPROM device occur via a standard I
using the DIMM’s SCL (clock) and SDA (data) signals, together with SA (2:0), which
provide eight unique DIMM/EEPROM addresses. Write protect (WP) is tied to ground on
the module, permanently disabling hardware write protect.
Speed
-40B
128MB, 256MB, 512MB (x64, SR): PC3200 184-Pin DDR UDIMM
75 ≤ f ≤ 133
CL = 2
Allowable OperatingClock Frequency (MHz)
11
Micron Technology, Inc., reserves the right to change products or specifications without notice.
75 ≤ f ≤ 133
CL = 2.5
General Description
©2005 Micron Technology, Inc. All rights reserved.
133 ≤ f ≤ 200
CL = 3
2
C bus