MT5VDDT872HG-265B2 Micron Technology Inc, MT5VDDT872HG-265B2 Datasheet - Page 4

• Manufacturer Part Number: MT5VDDT872HG-265B2
• Description: MODULE SDRAM DDR 64MB 200SODIMM
• Manufacturer: Micron Technology Inc

Specifications of MT5VDDT872HG-265B2

• Memory Type: DDR SDRAM
• Memory Size: 64MB
• Speed: 266MT/s
• Package / Case: 200-SODIMM
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Table 6:
PDF: 09005aef80a8e793/Source: 09005aef80a8e767
dd5c16_32x72h.fm - Rev. F 2/07 EN
CK1#, CK2, CK2#
CK0, CK0#, CK1,
DQS0–DQS8
WE#, CAS#,
DQ0–DQ63
DM0–DM8
BA0, BA1
SA0–SA2
CB0–CB7
Symbol
A0–A12
V
RAS#
CKE0
SDA
V
DDSPD
V
S0#
SCL
V
NC
REF
DD
SS
Pin Descriptions
Output
Output
Output
Output
Supply
Supply
Supply
Supply
Input/
Input/
Input/
Input/
Input
Input
Input
Input
Input
Input
Input
Input
Input
Type
–
Command inputs: RAS#, CAS#, and WE# (along with S#) define the command
being entered.
Clocks: CK and CK# are differential clock inputs. All address and control input
signals are sampled on the crossing of the positive edge of CK and negative edge
of CK#. Output data (DQs and DQS) is referenced to the crossings of CK and CK#.
Clock enable: CKE HIGH activates and CKE LOW deactivates the internal clock,
input buffers and output drivers.
Chip select: S# enables (registered LOW) and disables (registered HIGH) the
command decoder. All commands are masked when S# is registered HIGH. S# is
considered part of the command code.
Bank address: BA0 and BA1 define the device bank to which an ACTIVE, READ,
WRITE, or PRECHARGE command is being applied.
Address inputs: Provide the row address for ACTIVE commands, and the column
address and auto precharge bit (A10) for READ/WRITE commands, to select one
location out of the memory array in the respective device bank. A10 sampled
during a PRECHARGE command determines whether the PRECHARGE applies to
one device bank (A10 LOW, device bank selected by BA0, BA1) or all device banks
(A10 HIGH). The address inputs also provide the op-code during a MODE
REGISTER SET command. BA0 and BA1 define which mode register (mode register
or extended mode register) is loaded during the LOAD MODE REGISTER
command.
Data mask: DM is an input mask signal for write data. Input data is masked
when DM is sampled HIGH along with that input data during a WRITE access. DM
is sampled on both edges of DQS. Although DM pins are input-only, the DM
loading is designed to match that of DQ and DQS pins.
Serial presence-detect data: SDA is a bidirectional pin used to transfer
addresses and data into and out of the presence-detect portion of the module.
Serial clock for presence-detect: SCL is used to synchronize the presence-
detect data transfer to and from the module.
Presence-detect address inputs: These pins are used to configure the
presence-detect device.
Data strobe: Output with READ data, input with WRITE data. DQS is edge-
aligned with READ data, centered in WRITE data. Used to capture data.
Check bits.
Data input/output: Data bus.
SSTL_2 reference voltage.
Power supply: +2.5V ±0.2V. (-40B speed grade requires 2.6V ±0.1V)
Ground.
Serial EEPROM positive power supply: +2.3V to +3.6V.
No connect: These pins should be left unconnected.
128MB, 256MB: (x72, ECC, SR) 200-Pin DDR SODIMM
4
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Pin Assignments and Descriptions
Description
©2004 Micron Technology, Inc. All rights reserved.