MT8VDDT6464AG-335F4 Micron Technology Inc, MT8VDDT6464AG-335F4 Datasheet
MT8VDDT6464AG-335F4
Specifications of MT8VDDT6464AG-335F4
Related parts for MT8VDDT6464AG-335F4
MT8VDDT6464AG-335F4 Summary of contents
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DDR SDRAM UDIMM MT8VDDT3264A – 256MB MT8VDDT6464A – 512MB For component data sheets, refer to Micron’s Web site: Features • 184-pin, unbuffered dual in-line memory module (UDIMM) • Fast data transfer rates: PC2100, PC2700, or PC3200 • 256MB (32 Meg ...
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... MT8VDDT6464AG-262__ 512MB 512MB MT8VDDT6464AG-26A__ 512MB MT8VDDT6464AG-265__ MT8VDDT6464AY-265__ 512MB Notes: 1. Data sheets for the base devices can be found on Micron’s Web site. 2. All part numbers end with a two-place code (not shown) that designates component and PCB revisions. Consult factory for current revision codes. Example: MT8VDDT3264AY-335G6. ...
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Pin Assignments and Descriptions Table 5: Pin Assignments 184-Pin DDR UDIMM Front Pin Symbol Pin Symbol Pin Symbol Pin Symbol DQ17 47 REF 2 DQ0 25 DQS2 DQ1 ...
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... Power supply: +2.5V ±0.2V (-40B: +2.6V ±0.1V) Serial EEPROM positive power supply: +2.3V to +3.6V. SSTL_2 reference voltage (V Ground. – Do not use: These pins are not connected on these modules, but are assigned on other modules in this product family. – No connect: These pins are not connected on the module. 4 Pin Assignments and Descriptions /2) ...
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Functional Block Diagrams Figure 4: Functional Block Diagram – Standard Layout S0# DQS0 DM0 DQS1 DM1 DQS2 DM2 DQS3 DM3 BA0, BA1 A0–A11/A12 RAS# CAS# WE# CKE0 SCL WP V PDF: 09005aef80867ab3/Source: 09005aef80867a99 DD8C32_64x64A.fm - Rev. J 8/08 EN 256MB, ...
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Figure 5: Functional Block Diagram – Alternative and Reduced-Height Layout S0# DQS0 DM0 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQS1 DM1 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQS2 DM2 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 ...
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... The double data rate architecture is essentially a 2n-prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write access for DDR SDRAM modules effectively consists of a single 2n-bit- wide, one-clock-cycle data transfer at the internal DRAM core and two corresponding n- bit-wide, one-half-clock-cycle data transfers at the I/O pins ...
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Electrical Specifications Stresses greater than those listed in Table 7 may cause permanent damage to the module. This is a stress rating only, and functional operation of the module at these or any other conditions outside those indicated in each ...
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... Design Considerations Simulations Micron memory modules are designed to optimize signal integrity through carefully designed terminations, controlled board impedances, routing topologies, trace length matching, and decoupling. However, good signal integrity starts at the system level. Micron encourages designers to simulate the signal characteristics of the system’s memory bus to ensure adequate signal integrity of the entire memory system ...
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I Specifications DD Table 9: I Specifications and Conditions – 256MB (Die Revision ‘K’) DD Values are shown for the 256Mb (32 Meg x 8) component data sheet Parameter/Condition Operating one bank active-precharge current: (MIN); DQ, DM, and DQS inputs ...
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Table 10: I Specifications and Conditions – 256MB (All Other Die Revisions) DD Values are shown for the MT46V32M8 DDR SDRAM only and are computed from values specified in the 256Mb (32 Meg x 8) component data sheet Parameter/Condition Operating ...
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Table 11: I Specifications and Conditions – 512MB DD Values are shown for the MT46V64M8 DDR SDRAM only and are computed from values specified in the 512Mb (64 Meg x 8) component data sheet Parameter/Condition Operating one bank active-precharge current: ...
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Serial Presence-Detect Table 12: Serial Presence-Detect EEPROM DC Operating Conditions Parameter/Condition Supply voltage Input high voltage: Logic 1; All inputs Input low voltage: Logic 0; All inputs Output low voltage 3mA OUT Input leakage current GND ...
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Module Dimensions Figure 6: 184-Pin UDIMM – Standard Layout 2.0 (0.079) R (4X 2.5 (0.098) D (2X) 2.3 (0.091) TYP Pin 1 2.21 (0.087) TYP 1.27 (0.05) 1.0 (0.039) TYP 2.92 (0.115) TYP Pin 184 49.53 (1.95) TYP ...
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Figure 7: 184-Pin UDIMM – Alternative and Reduced-Height Layout 2.0 (0.079) R (4X 2.5 (0.098) D (2X) 2.31 (0.091) TYP Pin 1 2.21 (0.87) TYP 1.27 (0.05) 1.0 (0.039) TYP 2.92 (0.115) TYP Pin 184 49.53 (1.95) TYP ...