MT36HTS51272FY-667A3D3 Micron Technology Inc, MT36HTS51272FY-667A3D3 Datasheet
MT36HTS51272FY-667A3D3
Specifications of MT36HTS51272FY-667A3D3
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MT36HTS51272FY-667A3D3 Summary of contents
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... FBDIMM) – 14-pair northbound (data path from FBDIMM) • Fault tolerant; can work around a bad bit lane in each direction • High-density scaling with dual-rank modules (288 DDR2 SDRAM devices) per channel • SMBus interface to AMB for configuration register access • ...
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... Part Number MT36HTS51272FY-53E__ MT36HTS51272FY-667__ Notes: 1. All part numbers end with a two-place code (not shown), designating component and PCB revisions. Consult factory for current revision codes. Example: MT36HTS51272FY-53EC2. PDF: 09005aef822148b0/source: 09005aef82214898 HTS36C512x72F_1.fm - Rev. A 4/06 EN 240-Pin 4GB DDR2 SDRAM FBDIMM (DR, FB, x72) Peak Channel Throughput 8 ...
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Table of Contents Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of Figures Figure 1: 240-Pin FBDIMM (MO-256 R ...
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List of Tables Table 1: FBDIMM/DDR2 SDRAM Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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... Defines the electrical and mechanical requirements for 240-pin, PC2-4200/PC2-5300, 72-bit wide, fully buffered double data rate synchronous DRAM dual in-line memory modules (DDR2 SDRAM FBDIMMs). These DDR2 SDRAM FBDIMMs are intended for use as main memory when installed in systems such as servers and workstations. ...
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FBDIMM SPD Specification This section describes the serial presence-detect (SPD) values for FBDIMMs, refer- enced in the SPD “Specific Features” standard document. The SPD fields indicated in this specification will occur in the order presented in section 1.1 of ...
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... Micron Technology, Inc., reserves the right to change products or specifications without notice. 8 General Description Commodity DDR2 DDR2 DDR2 SDRAM Component devices DDR2 DDR2 Component DDR2 DDR2 Component DDR2 DDR2 Component modules AMB AMB • • • DDR2 DDR2 Component DDR2 DDR2 Component DDR2 DDR2 Component DDR2 DDR2 Component SMBus access to buffer registers © ...
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Functional Description Advanced Memory Buffer (AMB) The AMB reference design complies with the JEDEC standard, “FBDIMM Architecture and Protocol Specification.” expected that there will be AMB multiple vendors, which will offer at least the minimum functionality set forth ...
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AMB Interface Figure 3 illustrates the AMB and all of its interfaces. They consist of two FBDIMM links, one DDR2 channel, and an SMBus interface. Each FBDIMM link connects the AMB to a host memory controller or an adjacent FBDIMM. ...
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DDR2 Channel The AMB DDR2 channel supports direct connection to DDR2 SDRAM devices. The DDR2 channel supports two ranks of eight banks with 16 row/column-request, 64 data, and eight check-bit signals. There are two copies of address and command signals ...
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Therefore, the northbound data connection will exhibit the same peak theoretical throughput as a single DDR2 SDRAM channel. For example, when using DDR2-533 components, the peak theoretical bandwidth of the northbound data connection is 4.267 GB/s. Write data is transferred ...
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Figure 4: AMB Functional Block Diagram NORTH PLL 1x2 Ref Clock Reset# Reset Control Decoder and CRC Check Thermal Sensor Core Control and CRCs LAI Controller SMBus SMBus Controller PDF: 09005aef822148b0/source: 09005aef82214898 HTS36C512x72F_2.fm - Rev. A 4/06 EN 240-Pin 4GB ...
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Hot-Add The FBDIMM channel does not provide a mechanism to automatically detect and report the addition of a new FBDIMM south of the currently active last FBDIMM assumed the system will be notified through some means of the ...
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FBDIMM Functional Block Figure 5: FBDIMM Functional Block Diagram V SS CS0# DQS0 DQS0# DQ0 DQ1 DQ2 DQ3 DQS9 DQS9# DQ4 DQ5 DQ6 DQ7 DQS1 DQS1# DQ8 DQ9 DQ10 DQ11 DQS10 DQS10# DQ12 DQ13 DQ14 DQ15 DQS2 DQS2# DQ16 DQ17 ...
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Pin Assignments and Descriptions Table 4: 240-pin FBDIMM Pin Assignment Pin Front Pin Back Pin 1 V 121 122 123 124 V ...
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Figure 6: FBDIMM Pin Locations Front View PIN 1 Back View U10 U10 U11 U11 U12 U12 PIN 240 Indicates (1.8 Volt) PDF: 09005aef822148b0/source: 09005aef82214898 HTS36C512x72F_2.fm - Rev. A 4/06 EN ...
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Table 5: Pin Descriptions Pin Numbers 228 229 22, 25, 28, 31, 34, 37, 40, 48, 51, 54, 57, 60, 63, 66 23, 26, 29, 32, 35, 38, 41, 49, 52, 55, 58, 61, 64, 67 70, 73, 76, 79, ...
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Electrical Specifications Stresses greater than those listed in Table 6 may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the ...
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Table 8: Timing Parameters Parameter Electrical idle (EI) assertion pass-through timing EI de-assertion pass-through timing EI assertion duration FBDIMM command to DDR@ clock out that latches command FBDIMM command to DDR2 WRITE DDR2 READ to FBDIMM (last FBDIMM) Resample pass-through ...
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I Specifications and Conditions DD Assumptions for All Parameters • primary channel drive strength at 100 percent with de-emphasis at –6.5dB, secondary channel drive strength at 60 percent with de-emphasis at –3dB when enabled. • Address and data fields are ...
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Table 10: Reference Clock Input Specifications Parameter Reference clock frequency Rise time, fall time Voltage high Voltage low Absolute crossing point Relative crossing point Percent mismatch between rise and fall times T Duty cycle of reference clock Clock leakage current ...
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Differential Transmitter and Receiver Specifications Table 12: Differential Transmitter Output Specifications Parameter Differential peak-to-peak output voltage for large voltage swing Differential peak-to-peak output voltage for regular voltage swing Differential peak-to-peak output voltage for small voltage swing DC common code output ...
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Table 12: Differential Transmitter Output Specifications (Continued) Parameter MAX TX drift (resync mode) MAX TX drift (resample mode only) Bit error ratio Notes: 1. Specified at the package pins into a timing and voltage compliance test load as shown in ...
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Table 13: Differential Receiver Input Specifications Parameter Differential peak-to-peak input voltage for large voltage swing MAX single-ended voltage in EI condition MAX single-ended voltage in EI condition (DC only) MAX peak-to-peak differential voltage in EI condition Single-ended voltage (referencing V ...
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See Figure 3-8 and Figure 3-9 of the JEDEC specification. The single-pulse mask provides suf- ficient symbol energy for reliable RX reception. Each symbol must comply with both the sin- gle-pulse mask and the cumulative eyemask. 6. See Figure ...
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AMB Initialization The FBDIMM initialization process generally follows the top-to-bottom sequence of state transitions shown in Figure 7. The host must sequence the AMB devices through the disable, calibrate, (back to disable), training, testing, and polling states to move the ...
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Serial Presence-Detect SPD Clock and Data Conventions Data states on the SDA line can change only during SCL LOW. SDA state changes during SCL HIGH are reserved for indicating start and stop conditions, as shown in Figures 8 and 9 ...
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Figure 8: Data Validity SCL SDA Figure 9: Definition of Start and Stop SCL SDA Figure 10: Acknowledge Response from Receiver SCL from Master Data Output from Transmitter Data Output from Receiver PDF: 09005aef822148b0/source: 09005aef82214898 HTS36C512x72F_2.fm - Rev. A 4/06 ...
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Table 14: EEPROM Device Select Code The most significant bit (b7) is sent first Select Code Memory area select code (two arrays) Protection register select code Table 15: EEPROM Operating Modes Mode RW Bit Current address read Random address read ...
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Table 16: Serial Presence-Detect EEPROM DC Operating Conditions All voltages referenced to V Parameter/Condition Supply voltage Input high voltage: logic 1; all inputs Input low voltage: logic 0; all inputs Output low voltage 3mA OUT Input leakage current: ...
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Table 18: Serial Presence-Detect Matrix MT36HTS51272F “1”/“0”: Serial Data, “driven to HIGH”/“driven to LOW” Byte 0 CRC Range/SPD bytes total/bytes used 1 SPD revision 2 Key byte/DRAM device type 3 Voltage levels of this assembly 4 SDRAM addressing: Device rows/columns/banks ...
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Table 18: Serial Presence-Detect Matrix (Continued) MT36HTS51272F “1”/“0”: Serial Data, “driven to HIGH”/“driven to LOW” Byte Bits 7:4: ΔT 33 (DRAM case temperature difference between CASEMAX MAX case temperature and baseline MAX case temperature), the baseline MAX case temperature is ...
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Table 18: Serial Presence-Detect Matrix (Continued) MT36HTS51272F “1”/“0”: Serial Data, “driven to HIGH”/“driven to LOW” Byte 93 DT AMB LOS 94 PSI T-A DRAM-AF 95 PSIT-A AMB-AF 96 PSI D-A 97 PSI A-D 98 AMB TJMAX 99 Airflow imp/DRAM/heat spreader ...
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Module Dimensions All dimensions are in inches (millimeters). The dimensional diagram is for reference only. Refer to the MO document for complete design dimensions. Figure 12: 240-pin DDR2 FBDIMM Module Dimensions 2.63 (66.68) TYP. 0.069 (1.75) R (2X ...