MT18HTF25672PY-40EA2 Micron Technology Inc, MT18HTF25672PY-40EA2 Datasheet - Page 9

• Manufacturer Part Number: MT18HTF25672PY-40EA2
• Description: MODULE DDR2 2GB 240-DIMM
• Manufacturer: Micron Technology Inc

Specifications of MT18HTF25672PY-40EA2

• Memory Type: DDR2 SDRAM
• Memory Size: 2GB
• Speed: 400MT/s
• Package / Case: 240-DIMM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 11:
PDF: 09005aef80e5e752/Source: 09005aef80e5e626
HTF18C64_128_256x72.fm - Rev. E 3/07 EN
Parameter/Condition
Operating one bank active-precharge current:
t
commands; Address bus inputs are switching; Data bus inputs are switching
Operating one bank active-read-precharge current: I
BL = 4, CL = CL (I
(I
Address bus inputs are switching; Data pattern is same as I
Precharge power-down current: All device banks idle;
CKE is LOW; Other control and address bus inputs are stable; Data bus
inputs are floating
Precharge quiet standby current: All device banks idle;
CKE is HIGH, S# is HIGH; Other control and address bus inputs are stable;
Data bus inputs are floating
Precharge standby current: All device banks idle;
HIGH, S# is HIGH; Other control and address bus inputs are switching; Data
bus inputs are switching
Active power-down current: All device banks open;
t
inputs are stable; Data bus inputs are floating
Active standby current: All device banks open;
t
commands; Other control and address bus inputs are switching; Data bus
inputs are switching
Operating burst write current: All device banks open; Continuous burst
writes; BL = 4, CL = CL (I
t
bus inputs are switching; Data bus inputs are switching
Operating burst read current: All device banks open; Continuous burst
reads; I
t
valid commands; Address bus inputs are switching; Data bus inputs are
switching
Burst refresh current:
t
control and address bus inputs are switching; Data bus inputs are switching
Self refresh current: CK and CK# at 0V; CKE ≤ 0.2V; Other control and
address bus inputs are floating; Data bus inputs are floating
Operating bank interleave read current: All device banks interleaving
reads; I
t
HIGH, S# is HIGH between valid commands; Address bus inputs are stable
during deselects; Data bus inputs are switching
RC =
CK =
RAS MAX (I
RP =
RAS =
RFC (I
CK =
DD
),
t
t
t
t
t
RC (I
RP (I
DD
RCD =
CK (I
CK (I
t
OUT
OUT
RAS MAX (I
) interval; CKE is HIGH, S# is HIGH between valid commands; Other
DD
DD
DD
= 0mA; BL = 4, CL = CL (I
= 0mA; BL = 4, CL = CL (I
DD
DD
t
),
); CKE is HIGH, S# is HIGH between valid commands; Address
); CKE is LOW; Other control and address bus
DDR2 I
Values shown for MT47H128M4 DDR2 SDRAM only and are computed from values specified in the
512Mb (128 Meg x 4) component data sheet
RCD (I
),
),
t
t
RAS =
DD
RC =
t
RP =
), AL = 0;
DD
DD
t
),
DD
t
RC (I
); CKE is HIGH, S# is HIGH between valid commands;
t
RAS MIN (I
RP (I
t
DD
RP =
t
CK =
Specifications and Conditions – 1GB
), AL = 0;
DD
DD
t
CK =
),
t
); CKE is HIGH, S# is HIGH between valid
RP (I
t
CK (I
t
RRD =
DD
t
CK (I
DD
512MB, 1GB, 2GB (x72, ECC, SR) 240-Pin DDR2 SDRAM RDIMM
DD
DD
DD
); CKE is HIGH, S# is HIGH between valid
t
CK =
); CKE is HIGH, S# is HIGH between
), AL = 0;
); REFRESH command at every
), AL =
t
DD
RRD (I
),
t
CK (I
t
RC =
t
DD
RCD (I
DD
t
),
CK =
t
),
t
t
RC (I
RCD =
CK =
t
t
DD
RAS =
CK =
t
CK =
t
CK (I
DD
) - 1 x
t
CK (I
),
t
t
t
RCD (I
OUT
CK (I
CK =
t
t
DD
DD
t
t
CK (I
RAS MAX (I
RAS =
CK =
Fast PDN exit
MR[12] = 0
Slow PDN exit
MR[12] = 1
t
9
4W
DD
),
CK (I
= 0mA;
DD
t
DD
),
DD
CK (I
t
),
CK (I
t
t
DD
); CKE is
RAS =
); CKE is
RAS MIN
);
DD
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DD
DD
);
);
),
Symbol
I
I
I
I
I
I
I
DD
DD
DD
DD
DD
I
I
DD
DD
I
I
I
DD
DD
DD
DD
DD
4W
2Q
2N
3N
4R
2P
3P
0
1
5
6
7
-80E/
1,800 1,620 1,440 1,440
2,070 1,890 1,710 1,620
1,260 1,170
3,510 3,060 2,520 2,070
3,690 3,240 2,610 2,070
4,140 3,240 3,060 2,970
5,400 4,320 4,050 3,960
-800
126
900
990
720
216
126
©2003 Micron Technology, Inc. All rights reserved.
-667
126
810
900
630
216
126
I
DD
-53E -40E Units
Specifications
126
720
810
540
216
990
126
126
630
720
450
216
810
126
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA