ADZS-21262-1-EZEXT Analog Devices Inc, ADZS-21262-1-EZEXT Datasheet - Page 24

• Manufacturer Part Number: ADZS-21262-1-EZEXT
• Description: BOARD DAUGHTER FOR ADSP-21262
• Manufacturer: Analog Devices Inc

Specifications of ADZS-21262-1-EZEXT

• Accessory Type: DSP
• Silicon Manufacturer: Analog Devices
• Core Architecture: SHARC
• Features: Expansion Interface, High Speed Converter (HSC) Interface
• Kit Contents: Board Docs
• Silicon Family Name: SHARC
• Silicon Core Number: ADSP-21262
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: ADSP-21262
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366
Memory Read—Parallel Port
Use these specifications for asynchronous interfacing to memo-
ries (and memory-mapped peripherals) when the processor is
accessing external memory space.
Table 20. 8-Bit Memory Read Cycle
1
Parameter
Timing Requirements
t
t
t
Switching Characteristics
t
t
t
t
t
t
t
t
t
t
t
D = (The value set by the PPDUR Bits (5–1) in the PPCTL register) × t
H = t
F = 7 × t
On reset, ALE is an active high cycle. However, it can be configured by software to be active low.
DRS
DRH
DAD
ALEW
ADAS
RRH
ALERW
RWALE
ADAH
ALEHZ
RW
RDDRV
ADRH
DAWH
PCLK
1
1
1
PCLK
(if a hold cycle is specified, else H = 0)
(if FLASH_MODE is set, else F = 0)
AD7–0 Data Setup Before RD High
AD7–0 Data Hold After RD High
AD15–8 Address to AD7–0 Data Valid
ALE Pulse Width
AD15–0 Address Setup Before ALE Deasserted t
Delay Between RD Rising Edge to Next
Falling Edge
ALE Deasserted to Read Asserted
Read Deasserted to ALE Asserted
AD15–0 Address Hold After ALE Deasserted
ALE Deasserted to AD7–0 Address in High-Z
RD Pulse Width
AD7–0 ALE Address Drive After Read High
AD15–8 Address Hold After RD High
AD15–8 Address to RD High
AD15–8
AD7–0
ALE
WR
RD
NOTE: MEMORY READS ALWAYS OCCUR IN GROUPS OF FOUR BETWEEN ALE CYCLES. THIS FIGURE SHOWS ONLY
TWO MEMORY READS TO PROVIDE THE NECESSARY TIMING INFORMATION.
t
ALEW
t
VALID ADDRESS
VALID ADDRESS
ADAS
t
ADAH
t
Figure 17. Read Cycle for 8-Bit Memory Timing
ALEHZ
Rev. G | Page 24 of 56 | March 2011
t
ALERW
VALID ADDRESS
t
Min
3.3
0
2 × t
H + t
2 × t
F + H + 0.5
t
t
D – 2.0
F + H + t
H
D + t
DAWH
PCLK
PCLK
PCLK
PCLK
PCLK
PCLK
PCLK
PCLK
– 2.5
– 2.3
t
RW
PCLK
– 2.0
– 3.8
– 1.4
– 4.0
K and B Grade
VALID
DATA
– 2.3
t
RRH
Max
D + t
t
PCLK
t
DAD
VALID ADDRESS
PCLK
+ 3.0
t
DRS
– 5.0
VALID
DATA
t
t
RWALE
t
ADRH
DRH
t
Min
4.5
0
2 × t
t
H + t
2 × t
F + H + 0.5
t
t
D – 2.0
F + H + t
H
D + t
RDDRV
PCLK
PCLK
PCLK
PCLK
PCLK
PCLK
PCLK
– 2.5
– 2.3
PCLK
– 2.0
– 3.8
– 1.4
– 4.0
ADDRESS
ADDRESS
VALID
VALID
Y Grade
– 2.3
Max
D + t
t
PCLK
PCLK
+ 3.8
– 5.0 ns
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns