TMP86C909XB Toshiba, TMP86C909XB Datasheet - Page 127

• Manufacturer Part Number: TMP86C909XB
• Description: EMULATION CHIP FOR TMP86F SDIP
• Manufacturer: Toshiba

Specifications of TMP86C909XB

• Accessory Type: Adapter
• For Use With/related Products: TMP86F SDIP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

11.3 SEI Operation
11.3 SEI Operation
11.3.1 Controlling SEI clock polarity and phase
11.3.2 SEI data and clock timing
neously. The serial clock synchronizes the timing at which information on the two serial data lines are shifted or
sampled. Slave device can be selected individually using the slave select pin (
data on the SEI bus cannot be taken in.
During a SEI transfer, data transmission (serial shift-out) and reception (serial shift-in) are performed simulta-
When operating as the master devices, the
using two bits, CPHA and CPOL (SECR<CPHL,CPOL>).
fected).
the same clock phase and polarity.
that of the slave device to which to transfer.
eral devices. Refer to Section “" 11.5 SEI Transfer Formats "”.
The SEI clock allows its phase and polarity to be selected in software from four combinations available by
The clock polarity is set by CPOL to select between active-high or active-low (The transfer format is unaf-
The clock phase is set by CPHA. The master device and the slave devices to communicate with must have
If multiple slave devices with different transfer formats exist on the same bus, the format can be changed to
The programmable data and clock timing of SEI allows connection to almost all synchronous serial periph-
Table 11-2 Clock Phase and Polarity
CPHA
CPOL
SEI control register (SECR 002AH) bit 2
SEI control register (SECR 002AH) bit 3
SS
pin can be used to indicate multiple-master bus connection.
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SS
pin). For unselected slave devices,
TMP86F409NG