AD9911/PCBZ Analog Devices Inc, AD9911/PCBZ Datasheet - Page 28

• Manufacturer Part Number: AD9911/PCBZ
• Description: BOARD EVAL FOR AD9911
• Manufacturer: Analog Devices Inc
• Series: AgileRF™r

Specifications of AD9911/PCBZ

• Main Purpose: Timing, Direct Digital Synthesis (DDS)
• Utilized Ic / Part: AD9911
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Secondary Attributes: -
• Embedded: -
• Primary Attributes: -
• Lead Free Status / RoHS Status: Supplier Unconfirmed, Lead free / RoHS Compliant

AD9911
SYNCHRONIZING MULTIPLE AD9911 DEVICES
The AD9911 allows easy synchronization of multiple AD9911
devices. At power-up, the phase of SYNC_CLK may be offset
between multiple devices. There are three options (one
automatic mode and two manual modes) to compensate for this
offset and align the SYNC_CLK edges. These modes force the
internal state machines of multiple devices to a common state,
which aligns SYNC_CLKs.
Any mismatch in REF_CLK phase between devices results in a
corresponding phase mismatch on the SYNC_CLKs.
OPERATION
The first step is to program the master and slave devices for
their respective roles. Configure the master device by setting its
master enable bit (FR2 <6>). This causes the SYNC_OUT of the
master device to output a pulse whose pulse width equals one
system clock period and whose frequency equals ¼ of the
system clock frequency. Configuring device(s) as slaves is
performed by setting the slave enable bit (FR2 <7>).
AUTOMATIC MODE SYNCHRONIZATION
In automatic mode, synchronization is achieved by connecting
the SYNC_OUT pin on the master device to the SYNC_IN pin
of the slave device(s). Devices are configured as master or slave
through programming bits, accessible via the I/O port.
A configuration for synchronizing multiple AD9911 devices in
automatic mode is shown in the Application Circuits section. In
this configuration, the
and SYNC_IN to all devices.
In this mode, slave devices sample SYNC_OUT pulses from the
master device and a comparison of all state machines is made
by the auto-synchronization circuitry. If the slave device(s) state
machines are not identical to the master, the slave device(s)
state machines stall for one system clock cycle. This procedure
synchronizes the slave device(s) within three SYNC_CLK
periods.
Delay Time Between SYNC_OUT and SYNC_IN
When the delay between SYNC_OUT and SYNC_IN exceeds
one system clock period, phase offset bits (FR2 <1:0>) are used
to compensate. Without the compensation factor, a phase error
of 90°, 180°, or 270° might exist. The default state of these bits is
00, which implies that the SYNC_OUT of the master and the
SYNC_IN of the slave have a propagation delay of less than one
system clock period.
AD9510
provides coincident REF_CLK
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If the propagation time is greater than one system clock period,
the time should be measured and the appropriate offset
programmed. Table 21 describes the delays required per system
clock offset value.
Table 21.
System Clock
Offset Value
00
01
10
11
Automatic Synchronization Status Bit
If a slave device falls out of sync, the sync status bit is set. This
bit can be read through the I/O port bit (FR2 <5>). It clears
automatically when read. If the device reacquires sync before
the bit is read, the alarm will remain high. The bit does not
necessarily reflect the current state of the device. The status bit
can be masked by writing Logic 1 to the synchronization status
mask bit (FR2 <4>). When masked, the bit is held low.
MANUAL SOFTWARE MODE SYNCHRONIZATION
The manual software mode is enabled by setting the manual
synchronization bit (FR1 <0>). In this mode, the I/O update
that resets the Manual SW synchronization bit stalls the state
machine of the clock generator for one system clock cycle.
Stalling the clock generation state machine by one cycle changes
the phase relationship of SYNC_CLK between devices by one
system clock period (90°).
Note that the user may repeat this process until the devices have
the corresponding SYNC_CLK signals in the desired phase
relationship. The SYNC_IN input can be left floating since this
input has an internal pull-up. The SYNC_OUT is not used.
MANUAL HARDWARE MODE SYNCHRONIZATION
Manual hardware mode is enabled by setting the manual SW
synchronization bit (FR1 <1>). In this mode, the SYNC_CLK
stalls by one system clock cycle each time a rising edge is
detected on the SYNC_IN input. Stalling the SYNC_CLK state
machine by one cycle changes the phase relationship of
SYNC_CLK between devices by one system clock period (90°).
Note that the process can be repeated until the devices have
SYNC_CLK signals in the desired phase relationship. The
SYNC_IN input can be left floating since this input has an
internal pull-up. The SYNC_OUT is not used.
SYNC_OUT/SYNC_IN
Propagation Delay
0 ≤ delay ≤ 1
1 ≤ delay ≤ 2
2 ≤ delay ≤ 3
3 ≤ delay ≤ 4