AD9911/PCBZ Analog Devices Inc, AD9911/PCBZ Datasheet - Page 8

• Manufacturer Part Number: AD9911/PCBZ
• Description: BOARD EVAL FOR AD9911
• Manufacturer: Analog Devices Inc
• Series: AgileRF™r

Specifications of AD9911/PCBZ

• Main Purpose: Timing, Direct Digital Synthesis (DDS)
• Utilized Ic / Part: AD9911
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Secondary Attributes: -
• Embedded: -
• Primary Attributes: -
• Lead Free Status / RoHS Status: Supplier Unconfirmed, Lead free / RoHS Compliant

AD9911
Parameter
DATA LATENCY (PIPELINE DELAY) SINGLE-
DATA LATENCY (PIPELINE DELAY)
DATA LATENCY (PIPELINE DELAY) LINEAR
1
2
3
4
For the VCO frequency range of 160 MHz to 255 MHz, the appropriate setting for the VCO gain bit is dependent upon supply, temperature and process. Therefore, in a
production environment this frequency band must be avoided.
Data latency is reference to the I/O_UPDATE pin.
Data latency is fixed and the units are system clock (SYSCLK) cycles
Data latency is referenced to a profile change.
Frequency, Phase, and Amplitude Words to
Frequency Word to DAC Output with
Phase Offset Word to DAC Output with
Amplitude Word to DAC Output with
Frequency Word to DAC Output
Phase Offset Word to DAC Output
Amplitude Word to DAC Output
Frequency Rising/Falling Delta Tuning Word
Phase Offset Rising/Falling Delta Tuning
Amplitude Rising/Falling Delta Tuning Word
TONE MODE
MODULATION MODE
SWEEP MODE
DAC Output with Matched Latency Enabled
Matched Latency Disabled
Matched Latency Disabled
Matched Latency Disabled
to DAC Output
Word to DAC Output
to DAC Output
2, 3
4
4
Min
29
29
25
17
34
29
21
41
37
29
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Typ
Max
Unit
SYSCLK
cycles
SYSCLK
cycles
SYSCLK
cycles
SYSCLK
cycles
SYSCLK
Cycles
SYSCLK
Cycles
SYSCLK
Cycles
SYSCLK
Cycles
SYSCLK
Cycles
SYSCLK
Cycles
Test Conditions/Comments