AD9911/PCBZ Analog Devices Inc, AD9911/PCBZ Datasheet - Page 36

• Manufacturer Part Number: AD9911/PCBZ
• Description: BOARD EVAL FOR AD9911
• Manufacturer: Analog Devices Inc
• Series: AgileRF™r

Specifications of AD9911/PCBZ

• Main Purpose: Timing, Direct Digital Synthesis (DDS)
• Utilized Ic / Part: AD9911
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Secondary Attributes: -
• Embedded: -
• Primary Attributes: -
• Lead Free Status / RoHS Status: Supplier Unconfirmed, Lead free / RoHS Compliant

AD9911
CHANNEL REGISTER MAP
Table 25.
Register Name
(Address)
Channel
Function
(0x03)
Channel
Frequency Tuning
Word 0
(0x04)
Channel Phase
Offset Word 0
(CPOW0) (0x05)
Amplitude
Control (ACR)
(0x06)
Linear Sweep
Ramp Rate
(0x07)
LSR Rising Delta
(RDW) (0x08)
LSR Falling Delta
(FDW) (0x09)
1
2
There are four sets of channel registers and profile registers, one per channel. This is not shown in the channel or profile register maps because the addresses of all
channel registers and profile registers are the same for each channel. Therefore, the channel enable bits determine if the channel registers and/or profile registers are
written to or not.
The clear accumulator bit is set after a master reset. It self clears when an I/O update is asserted.
1
(CTW0)
1
(CFR)
1
(LSR)
1
1
1
Bit
Range
<7:0>
<15:8>
<23:16>
<7:0>
<15:8>
<23:16>
<31:24>
<7:0>
<15:8>
<7:0>
<15:8>
<23:16>
<7:0>
<15:8>
<7:0>
<15:8>
<23:16>
<31:24>
<7:0>
<15:8>
<23:16>
<31:24>
Bit 7 (MSB)
Digital power-
down
Linear sweep
no-dwell
Increment/decrement
step size <15:14>
Amplitude frequency
phase select <23:22>
Open <15:14>
DAC
power
down
Linear
sweep
enable
Bit 6
Open
Bit 5
Matched
pipe delays
active
Load SRR
at I/O
Update
Linear sweep falling ramp rate (FSRR) <15:8>
Rev. 0 | Page 36 of 44
Linear sweep rising ramp rate (RSRR) <7:0>
Frequency Tuning Word 0 <23:16>
Frequency Tuning Word 0 <31:24>
Frequency Tuning Word 0 <15:8>
Frequency Tuning Word 0 <7:0>
Bit 4
Auto clear
sweep
accumulator
Open
Amplitude
multiplier
enable
Amplitude ramp rate <23:16>
Open <21:19>
Falling delta word <23:16>
Falling delta word <31:24>
Rising delta word <23:16>
Rising delta word <31:24>
Falling delta word <15:8>
Rising delta word <15:8>
Falling delta word <7:0>
Rising delta word <7:0>
Amplitude scale factor
Phase Offset Word 0
Bit 3
Clear sweep
accumulator
Open
Phase Offset Word 0 <13:8>
Ramp-up/
ramp-down
enable
Load ARR at I/O
update
Bit 2
Auto clear
phase
accumulator
Must be 0
Data align bits for SpurKiller mode
Bit 1
Clear phase
accumulator
<18:16>
DAC full-scale current
control <9:8>
Amplitude scale
factor <9:8>
2
(LSB)
Bit 0
Sine
wave
output
enable
Default
Value
0x02
0x03
0x00
0x00
0x00
0x00
0x00
0x00
–
–
–
–
–
–
–
–
–
–
–