DS32EV100-EVK National Semiconductor, DS32EV100-EVK Datasheet - Page 2

• Manufacturer Part Number: DS32EV100-EVK
• Description: KIT EVALUATION FOR DS32EV100
• Manufacturer: National Semiconductor

Specifications of DS32EV100-EVK

• Main Purpose: Interface, Cable Equalizer
• Utilized Ic / Part: DS32EV100
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Secondary Attributes: -
• Embedded: -
• Primary Attributes: -

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NSID
DS32EV100SD
DS32EV100SDX
HIGH SPEED DIFFERENTIAL I/O
IN−
IN+
OUT−
OUT+
EQUALIZATION CONTROL
BST_2
BST_1
BST_0
POWER
V
GND
DAP
OTHER
NC
Pin Name
DD
Pin Diagram
Ordering Information
Pin Descriptions
Note: I = Input, O = Output
2, 6, 9, 10,
Pin #
PAD
11
12
14
13
4
3
7
8
5
1
LVCMO
O, CML Inverting and non-inverting CML differential outputs from the equalizer. An on-chip 50Ω
I, CML
Power
Power
Power
Type
I/O,
I,
S
14-Pin LLP Package (3 mm x 4 mm x 0.8 mm, 0.5 mm pitch)
Package Type, Qty Size
14–pin LLP (3 mm x 4 mm x 0.8 mm, 0.5 mm pitch, reel of 1000
14–pin LLP (3 mm x 4 mm x 0.8 mm, 0.5 mm pitch, reel of 4500
Inverting and non-inverting CML differential inputs to the equalizer. An on-chip 100Ω terminating
resistor is connected between IN+ and IN−. Refer to Figure 4.
terminating resistor connects OUT+ to V
BST_2, BST_1, and BST_0 select the equalizer strength. BST_2 is internally pulled high. BST_1
and BST_0 are internally pulled low.
V
path. A 0.01μF bypass capacitor should be connected between each V
Ground reference. GND should be tied to a solid ground plane through a low impedance path.
Ground reference. The exposed pad at the center of the package must be connected to ground
plane of the board.
Reserved. Leave no Connect.
DD
= 2.5V ±5% or 3.3V ±10%. V
See NS Package Number SQA14A
2
DD
pins should be tied to V
DD
Description
and OUT− to V
20206503
DD
DD
.
plane through low inductance
DD
Package ID
SDA14A
SDA14A
pin to GND planes.