SERDES03-40USB/NOPB National Semiconductor, SERDES03-40USB/NOPB Datasheet
SERDES03-40USB/NOPB
Specifications of SERDES03-40USB/NOPB
Related parts for SERDES03-40USB/NOPB
SERDES03-40USB/NOPB Summary of contents
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... User selectable clock edge for parallel data on both Transmitter and Receiver Block Diagram TRI-STATE ® registered trademark of National Semiconductor Corporation. © 2007 National Semiconductor Corporation ■ Internal DC Balancing encode/decode – Supports AC- coupling interface with no external coding required ■ Individual power-down controls for both Transmitter and Receiver ■ ...
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... Absolute Maximum Ratings If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage ( LVCMOS/LVTTL Input Voltage LVCMOS/LVTTL Output Voltage LVDS Receiver Input Voltage LVDS Driver Output Voltage LVDS Output Short Circuit Duration ...
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Symbol Parameter LVDS DC SPECIFICATIONS V Differential Threshold High TH Voltage V Differential Threshold Low TL Voltage I Input Current IN R Differential Internal T Termination Resistance V Output Differential Voltage OD (D )–(D ) OUT+ OUT− ΔV Output Differential ...
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Symbol Parameter I Deserializer (Rx) DDR Total Supply Current (includes load current) Deserializer (Rx) Total Supply Current (includes load current) I Deserializer (Rx) DDRZ Supply Current Power-down Serializer Timing Requirements for TCLK Over recommended operating supply and temperature ranges unless ...
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Symbol Parameter t ROUT (7:0) Setup Data to ROS RCLK (Group 1) t ROUT (7:0) Hold Data to ROH RCLK (Group 1) t ROUT (15:8) Setup Data to ROS RCLK (Group 2) t ROUT (15:8) Hold Data to ROH RCLK ...
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AC Timing Diagrams and Test Circuits FIGURE 3. Serializer LVDS Output Load and Transition Times www.national.com FIGURE 1. Serializer Input Checker-board Pattern FIGURE 2. Deserializer Output Checker-board Pattern FIGURE 4. Serializer Input Clock Transition Times 6 20208002 20208003 20208004 20208006 ...
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FIGURE 5. Serializer Setup/Hold Times FIGURE 6. Serializer TRI-STATE Test Circuit and Delay 7 20208007 20208008 www.national.com ...
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FIGURE 7. Serializer PLL Lock Time, and TPWDNB TRI-STATE Delays FIGURE 9. Transmitter Output Eye Opening (TxOUT_E_O) www.national.com FIGURE 8. Serializer Delay 8 20208009 20208010 20208015 ...
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VOD = (D ) – OUT+ OUT - Differential output signal is shown – (D OUT+ FIGURE 11. Deserializer LVCMOS/LVTTL Output Load and Transition Times ), device in Data Transfer mode. OUT - FIGURE 10. ...
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Note: C includes instrumentation and fixture capacitance within ROUT[23:0] L FIGURE 13. Deserializer TRI-STATE Test Circuit and Timing FIGURE 14. Deserializer PLL Lock Times and RPWDNB TRI-STATE Delay www.national.com 20208013 10 20208014 ...
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RxIN_TOL_L is the ideal noise margin on the left of the figure, with respect to ideal. RxIN_TOL_R is the ideal noise margin on the right of the figure, with respect to ideal. FIGURE 16. Receiver Input Tolerance (RxIN_TOL) and Sampling ...
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DS99R103 Serializer Pin Descriptions Pin # Pin Name I/O LVCMOS PARALLEL INTERFACE PINS 4-1, DIN[23:0] LVCMOS_I 48-44, 41-32, 29-25 10 TCLK LVCMOS_I CONTROL AND CONFIGURATION PINS 9 TPWDNB LVCMOS_I 18 DEN LVCMOS_I 23 PRE LVCMOS_I 11 TRFB LVCMOS_I 12 VODSEL ...
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DS99R103 Pin Diagram Serializer - DS99R103 TOP VIEW 13 20208019 www.national.com ...
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DS99R104 Deserializer Pin Descriptions Pin # Pin Name I/O LVCMOS PARALLEL INTERFACE PINS 25-28, ROUT[7:0] LVCMOS_O 31-34 13-16, ROUT[15:8] LVCMOS_O 21-24 3-6, ROUT[23:16] LVCMOS_O 9-12 18 RCLK LVCMOS_O CONTROL AND CONFIGURATION PINS 43 RRFB LVCMOS_I 48 REN LVCMOS_I 1 RPWDNB ...
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DS99R104 Pin Diagram Deserializer - DS99R104 TOP VIEW 15 20208020 www.national.com ...
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Functional Description The DS99R103 Serializer and DS99R104 Deserializer chipset is an easy-to-use transmitter and receiver pair that sends 24-bits of parallel LVCMOS data over a single serial LVDS link from 72 Mbps to 960 Mbps throughput. The DS99R103 transforms a ...
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LOCK pin to determine whether data on the ROUT is valid. POWERDOWN The Powerdown state is a low power sleep mode that the Se- rializer and Deserializer may use to reduce power when no data is being ...
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For a graphical representation of noise margin, please see Figure 16. TRANSMISSION MEDIA The Serializer and Deserializer can be used in point-to-point configuration, through a PCB trace, or through twisted pair cable point-to-point configuration, the transmission me- dia ...
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FIGURE 18. DS99R103 Typical Application Connection 19 20208021 www.national.com ...
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FIGURE 19. DS99R104 Typical Application Connection www.national.com 20 20208022 ...
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Truth Tables TPWDNB (Pin 9) (Pin 18 RPWDNB REN (Pin 1) (Pin 48 TABLE 1. DS99R103 Serializer Truth Table DEN Tx PLL Status (Internal ...
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Physical Dimensions Ordering Information NSID DS99R103TVS 48 Lead TQFP style, 7.0 X 7.0 X 1.0 mm, 0.5 mm pitch DS99R103TVSX 48 Lead TQFP style, 7.0 X 7.0 X 1.0 mm, 0.5 mm pitch, 1000 std reel DS99R104TVS 48 Lead TQFP ...
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Physical Dimensions inches (millimeters) unless otherwise noted Ordering Information NSID DS99R103TSQ 48 Lead LLP style, 7.0 X 7.0 X 0.8 mm, 0.5 mm pitch DS99R103TSQX 48 Lead LLP style, 7.0 X 7.0 X 0.8 mm, 0.5 mm pitch, 1000 std ...
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