CLINK3V48BT-133 National Semiconductor, CLINK3V48BT-133 Datasheet
CLINK3V48BT-133
Specifications of CLINK3V48BT-133
Related parts for CLINK3V48BT-133
CLINK3V48BT-133 Summary of contents
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... National Semiconductor Channel Link Design Guide June 2006 Introduction Page 2 Design Guidelines Pages Cables & Connectors Page 6 Chip Operation Pages Evaluation Kits Pages 11 Speed vs Cable Length Pages ...
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... Channel Link LVDS SerDes “Virtual Ribbon Cable” Introduction National Semiconductor’s DS90CR2xx and DS90CR4xx Channel Link serializers/deserializers (SerDes) are among the easiest to use SerDes in the market. Unlike most SerDes, Channel Link serialize wide buses, require no synchronization training characters or patterns, re- quire no clock source at the receiver end ...
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... See Note 1 -40 to +85°C TSSOP-56 See Note 1 -10 to +70°C TSSOP-56 CLINK3V28BT-85 -10 to +70°C TSSOP-56 CLINK3V28BT-85 -10 to +70°C TQFP-100 CLINK3V48BT-112 -10 to +70°C TQFP-100 CLINK3V48BT-112 -10 to +70°C TQFP-100 CLINK3V48BT-112 -10 to +70°C TQFP-100 CLINK3V48BT-112 -10 to +70°C TQFP-100 CLINK3V48BT-133 -10 to +70°C TQFP-100 CLINK3V48BT-133 ...
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Design Guidelines General Information 48:8 28 MHz 21 MHz Hex 10:1 24:1 DS90C241/124 18 MHz 16 MHz 10:1 10:1 Quad 4:1 4:1 100 250 Bus Topologies Channel Link ...
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General Printed Circuit Board (PCB) Recommen- dations • Use at least 4 PCB board layers (LVDS signals, ground, power, and TTL signals). • Minimize pair-to-pair skew between LVDS clock and data • Use proper power supply bypassing such that PLL ...
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Design Guidelines Cables & Connectors Twinax cable construction Unshielded twisted pair (UTP) cable construction Connector pin assignment for low skew. Top-good; bottom-bad. 6 Cables Channel Link SerDes can be used over a wide variety of balanced, 100-Ohm differen- tial cables ...
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General Power/Ground Recommendations A solid power/ground system is the foundation on which a reliable interconnect system is built. Design circuit board layout and stack-up for the system to provide noise-free power to the device. Good layout practice will separate high ...
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Design Guidelines Inputs & Outputs LVDS Termination LVDS termination is required. Choose the termination resistor value RL to match the loaded differential impedance of the transmission line. In point-to-point applications, the termination value is typically 100 Ohms. Place a termination ...
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Probing LVDS Signals LVDS signals are high speed, low swing signals. Improper probing can result in deceiving results since the probe and/or scope can filter high speed components of the signal. Using a >1 GHz bandwidth scope (such as the ...
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Design Review Check Your Design for High Performance Design Tip Overview Channel Link are robust, easy-to-use SerDes, but to get the best performance from your interconnect design, it’s a good idea to review your design for best practices. • Pair-to-Pair ...
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... CLINK3V28BT-85, CLINK3V48BT-112, CLINK3V48BT-133 Evaluation Boards Three Channel Link evaluation kits are available from National Semiconductor and its distributors. With just these three kits, any Channel Link SerDes chipset can be evalu- ated since 28- and 21- bit Channel Link chipsets are pin compatible (see table at right for more info) ...
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Channel Link Operation Power Up/Down & Floating Inputs Device Name Supply Voltage Compression Ratio DS90CR211 5 † DS90CR212 5 † DS90CR213 5 DS90CR214 5 DS90CR215 3.3 DS90CR216 3.3 † DS90CR216A 3.3 DS90CR217 3.3 DS90CR218 3.3 † DS90CR218A 3.3 DS90CR281 5 ...
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All Inputs Floating/Failsafe Device Name Clock Outputs Data Outputs DS90CR211 High-Z High-Z † DS90CR212 High High † DS90CR213 High-Z High-Z DS90CR214 High High DS90CR215 High-Z High-Z DS90CR216 High High † DS90CR216A High High DS90CR217 High-Z High-Z DS90CR218 High High † ...
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Channel Link Operation DS90CR48x Deskew Deskew The 48-bit Channel Link deskew function compensates for fixed pair-to-pair skew such as the fixed skew in cables, connectors, and PCB traces. Deskew operation is fundamentally different in the DS90CR482/484 versus the DS90CR486. With ...
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Receiver Skew Margin (RSKM) & Pair-to-Pair Skew The main consideration for Channel Link SerDes performance over cable is pair-to-pair skew. Unlike other SerDes, Channel Link SerDes send data and clock over multiple pairs, lowering the data rate per pair and ...
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Channel Link Operation Calculating RSKM Link Margin Without Deskew RSKM is very similar to the receiver jitter tolerance specifications of other SerDes devices, except: • RSKM already includes serializer data output jitter. Clock jitter is not included, however, and therefore ...
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Cable pair-to-pair skew is often the limiting factor in Channel Link designs. Therefore, the DS90CR48x 48-bit Channel Link chipsets include a feature to deskew the cable. After deskew operation is performed using these chipsets, only pair-to-pair skew that exceeds the ...
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Data Rate vs. Cable Length 48-bit Channel Link All 48 LVTTL inputs switching, however, one LVDS channel was monitored for BER. 18 Tests conducted in laboratory conditions using Channel Link evaluation boards and 3M MDR cable assemblies. ...
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Tests conducted in laboratory conditions using Channel Link evaluation boards and 3M MDR cable assemblies. 21- & 28- bit Channel Link 1 ...
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... Phone: 81-3-5639-7560 © National Semiconductor Corporation, 2006. National Semiconductor, , WEBENCH, and LLP are registered trademarks and LMH is a trademark of National Semiconductor Corporation. LVDS Owner’s Manual–3rd Edition Changes to the June 2006 document since the last version: Page 14: Valid deskew pattern relaxed from three LVDS edge transitions (May 2005) to one LVDS edge transition (June 2006) per clock cycle ...