CLINK3V48BT-133 National Semiconductor, CLINK3V48BT-133 Datasheet
CLINK3V48BT-133
Specifications of CLINK3V48BT-133
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CLINK3V48BT-133 Summary of contents
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... The DS90CR485 is intended for use with the DS90CR486 Channel-Link receiver also backward compatible with other Channel-Link receiver such as the DS90CR482 and DS90CR484. Generalized Block Diagram © 2003 National Semiconductor Corporation For more details, please refer to the “Applications Informa- tion” section of this datasheet. Features 6.384 Gbps throughput ...
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... Absolute Maximum Ratings If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage ( Supply Voltage (V ) CC3 LVCMOS/LVTTL Input Voltage −0. LVDS Output Voltage LVDS Short Circuit Duration Maximum Package Power Dissipation 100 TQFP Package Derate TQFP Package 23.8mW/˚ ...
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Recommended Input Requirements Over recommended operating supply and temperature ranges unless otherwise specified. (Note 2) Symbol TCIP TxCLK IN Period (Figure 4) TCIH TxCLK in High Time (Figure 4) TCIL TxCLK in Low Time (Figure 4) TCIT TxCLK IN Transition ...
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AC Timing Diagrams Note 7: The worst case test pattern produces a maximum toggling of digital circuits, LVCMOS/LVTTL I/O. www.national.com FIGURE 1. “Worst Case” Test Pattern (Note 7) FIGURE 2. LVDS Output Load and Transition Times FIGURE 3. Input Clock ...
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AC Timing Diagrams (Continued) FIGURE 6. Phase Lock Loop Set Time (V FIGURE 5. Setup/Hold with CLKIN ≥ 2.37V) CC FIGURE 7. Power Down Delay 5 20019553 20019519 20019521 www.national.com ...
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AC Timing Diagrams www.national.com (Continued) FIGURE 8. Input to Output Latency 6 20019552 ...
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DS90CR485 Pin Description—Channel Link Serializer Pin Name I/O No. of Pins D0-D23 I 24 LVCMOS/LVTTL level single-ended inputs. 3V tolerant when V Note, external pull-down resistor of 1kΩ is required on all unused input data pins. CLKIN I 1 LVCMOS/LVTTL ...
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DS90CR485 Pin Description—Channel Link Serializer Pin Name I/O No. of Pins TEST1 I 1 This pin should be tied low or left open. Tied to high (V future use. (Note 9) TEST2 I 1 This pin should be tied low ...
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LVDS Interface (Continued) FIGURE 10. 48 LVCMOS/LVTLL Inputs Mapped to 8 LVDS Outputs (DC Balance Mode- Enabled; BAL = High) (E1 - Falling Edge Rising Edge) 9 20019556 www.national.com ...
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DS90CR483 Inputs Mapped to DS90CR485 Inputs DS90CR483 Tx Input TxIN0 TxIN1 TxIN2 TxIN3 TxIN4 TxIN5 TxIN6 TxIN7 TxIN8 TxIN9 TxIN10 TxIN11 TxIN12 TxIN13 TxIN14 TxIN15 TxIN16 TxIN17 TxIN18 TxIN19 TxIN20 TxIN21 TxIN22 TxIN23 TxIN24 TxIN25 TxIN26 TxIN27 TxIN28 TxIN29 TxIN30 ...
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Applications Information PRE-EMPHASIS Adds extra current during LVDS logic transition to reduce cable loading effects. Pre-emphasis strength is set via a DC voltage level applied from min to max (0.75V to V “PRE” pin. A higher input voltage on the ...
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Applications Information POWER-UP SEQUENCE AND 3V TOLERANT The DS90CR485 inputs provide an option for 3.3V tolerant. If this is required, the V pin must be connected to a 3.3V CC3V rail. Also when power is applied to the transmitter, V ...
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Applications Information j Use the S/2S/3S rule in spacings (S = space between the pair space between the pairs space to TTL signal) j Minimize the number of VIA j Use differential connectors when operating above ...
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Applications Information CONFIGURATION 1 DS90CR481/483 and DS90CR484 with DC Balance ON (BAL = High, 33MHz to 80MHz) − The DS_OPT pin at the input of the transmitter DS90CR481/483 must be applied low for a minimum of four clock cycles in ...
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Pin Diagram Transmitter-DS90CR485 (Top View) 15 20019506 www.national.com ...
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... NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant ...