ADC08D1020DEV/NOPB National Semiconductor, ADC08D1020DEV/NOPB Datasheet - Page 5

• Manufacturer Part Number: ADC08D1020DEV/NOPB
• Description: BOARD DEV FOR ADC08D1020
• Manufacturer: National Semiconductor
• Series: PowerWise®r

Specifications of ADC08D1020DEV/NOPB

• Number Of Adc's: 2
• Number Of Bits: 8
• Sampling Rate (per Second): 1G
• Data Interface: Serial
• Inputs Per Adc: 1 Differential
• Input Range: 870 mVpp
• Power (typ) @ Conditions: 1.6W @ 1GSPS
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: ADC08D1020
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ADC08D1020DEV

3.8 ADC Analog Inputs
The analog inputs (I- and Q-channel) are provided
through SMA connectors on the front edge of the board
and are single-ended.
capable of accepting an AC- or DC-coupled input signal.
The Q-channel may be AC-coupled only.
Single-ended to differential input signal conversion is
performed by a Mini-Circuits Balun (ADTL2-18) for the
AC-coupled path. A LMH6555 Differential Op-Amp is
used to DC couple the input signal. Software-controlled
Teledyne RF relays are used to switch the signal path
from AC- to DC-coupled.
3.9 Trigger Input
A trigger input is provided on the front panel through a
SMA connector. This signal is connected to the FPGA
via a Schmitt trigger and is TTL compatible with 5V
tolerance.
provided so the user may develop his own FPGA
functionality if desired.
3.10 Status Indicators
The Following Status Indicators (LEDs) are provided on
the front edge of the board, Figure2:
_________________________________________________________________________________________________________________________
Refer to Figure 3 for the location of the power
connection, signal input and USB port.
4.0 Quick Start
Figure 2. Component placement and front panel
Expansion
MICTOR
Header
Header
Header
Switch
JTAG
PWR
PWR
Input
This input has no functionality, and is
The ADC I-channel input is
Figure 3. Development board overview
This is a brief summary of the name, abbreviation and
description of the status LEDs:
3.11 Debug
A Mictor Logic Analyzer Header is provided along with
test-point headers both of which are connected to the
FPGA. This allows monitoring of captured data and
critical signals during board debug. A JTAG header is
also provided to allow further FPGA development.
Name
Standby
Trigger
Over-
range
Clock
Power-on
Upload
Sample
FPGA
RDY/IDLE
Abbr.
STB
TRG
OVR
CLK
PWR
UPL
SMP
IDL
Table 2. Status Indicators
Description
All switching regulators powered
down
Trigger input indicator
Over-range indicator
Clock active indicator (blinks)
12V-30V power
Data is being uploaded to PC
Data is being captured by FPGA
FPGA is programmed and IDLE
Q-CH. Input
Trigger
I-CH. Input
Clock
Input
Input
Analog
Analog
Status
LEDS
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