ADC08D1020DEV/NOPB National Semiconductor, ADC08D1020DEV/NOPB Datasheet
ADC08D1020DEV/NOPB
Specifications of ADC08D1020DEV/NOPB
Related parts for ADC08D1020DEV/NOPB
ADC08D1020DEV/NOPB Summary of contents
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... LQFP and op- ≤ erates over the Industrial (-40°C range. Ordering Information Industrial Temperature Range (-40°C < T ADC08D1020CIYB ADC08D1020CIYB/NOPB ADC08D1020DEV © 2009 National Semiconductor Corporation ADC08D1020 Features ■ Single +1.9V ±0.1V Operation ■ Interleave Mode for 2x Sample Rate ■ Multiple ADC Synchronization Capability ■ ...
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Block Diagram www.national.com 2 20206253 ...
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Pin Configuration Note: The exposed pad on the bottom of the package must be soldered to a ground plane to ensure rated performance. 3 20206201 www.national.com ...
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Pin Descriptions and Equivalent Circuits Pin Functions Pin No. Symbol 3 OutV / SCLK 29 PDQ OutEdge / DDR / 4 SDATA DCLK_RST / 15 DCLK_RST CAL www.national.com Equivalent Circuit Output Voltage Amplitude and Serial Interface Clock. ...
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Pin Functions Pin No. Symbol FSR/ALT_ECE/ 14 DCLK_RST- 127 CalDly / DES / SCS 18 CLK+ 19 CLK− I− Q− IN Equivalent Circuit Full Scale Range Select, ...
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Pin Functions Pin No. Symbol V 7 CMO 126 CalRun R 32 EXT 34 Tdiode_P 35 Tdiode_N 41 ECE 52 DRST_SEL www.national.com Equivalent Circuit Common Mode Voltage. This pin is the common mode output in d.c. coupling ...
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Pin Functions Pin No. Symbol DI7− / DQ7− DI7+ / DQ7 DI6− / DQ6− DI6+ / DQ6 DI5− / DQ5− DI5+ / ...
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Pin Functions Pin No. Symbol 13, 16, 17, 20 25, 28, 33, 128 40, 51, 62, 73, 88, 99 110, 121 12, GND 21, 24, 27 42, 53, 64, 74, ...
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... Absolute Maximum Ratings (Note 1, Note 2) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage ( Supply Difference Voltage on Any Input Pin (Except −0.15V Voltage (Maintaining Common Mode) Ground Difference |GND - DR GND| ...
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Symbol Parameter SNR Signal-to-Noise Ratio THD Total Harmonic Distortion 2nd Harm Second Harmonic Distortion 3rd Harm Third Harmonic Distortion SFDR Spurious-Free dynamic Range IMD Intermodulation Distortion Out of Range Output Code (In addition to OR Output high) NORMAL MODE (Non ...
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Symbol Parameter Analog Input Capacitance, Normal operation (Note 10, Note 11 Analog Input Capacitance, DES Mode (Note 10, Note R Differential Input Resistance IN ANALOG OUTPUT CHARACTERISTICS Common Mode Output V CMO Voltage Common Mode Output TC V ...
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Symbol Parameter DIGITAL OUTPUT CHARACTERISTICS LVDS Differential Output V OD Voltage Change in LVDS Output Swing ΔV O DIFF Between Logic Levels Output Offset Voltage V OS See Figure 1 Output Offset Voltage V OS See Figure 1 Output Offset ...
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Symbol Parameter AC ELECTRICAL CHARACTERISTICS Maximum Input Clock f CLK (max) Frequency Minimum Input Clock f CLK (min) Frequency Input Clock Duty Cycle t Input Clock Low Time CL t Input Clock High Time CH DCLK Duty Cycle t Setup ...
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Symbol Parameter Serial Data to Serial Clock t SH Rising Hold Time CS to Serial Clock Rising t SCS Setup Time CS to Serial Clock Falling Hold t HCS Time Serial Clock Low Time Serial Clock High Time t Calibration ...
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Specification Definitions APERTURE (SAMPLING) DELAY is the amount of delay, measured from the sampling edge of the Clock input, after which the signal present at the input pin is sampled inside the device the variation in aperture delay ...
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SPURIOUS-FREE DYNAMIC RANGE (SFDR) is the differ- ence, expressed in dB, between the rms values of the input signal at the output and the peak spurious ...
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Transfer Characteristic FIGURE 2. Input / Output Transfer Characteristic 17 20206222 www.national.com ...
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Timing Diagrams FIGURE 3. ADC08D1020 Timing — SDR Clocking in 1:2 Demultiplexed Mode FIGURE 4. ADC08D1020 Timing — DDR Clocking in 1:2 Demultiplexed and Normal Mode www.national.com 18 20206214 20206259 ...
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FIGURE 5. ADC08D1020 Timing — DDR Clocking in Non-Demultiplexed and Normal Mode FIGURE 6. Serial Interface Timing FIGURE 7. Clock Reset Timing in DDR Mode 19 20206261 20206219 20206220 www.national.com ...
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FIGURE 8. Clock Reset Timing in SDR Mode with OUTEDGE Low FIGURE 9. Clock Reset Timing in SDR Mode with OUTEDGE High FIGURE 10. Power-up Calibration and On-Command Calibration Timing www.national.com 20 20206223 20206224 20206225 ...
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Typical Performance Characteristics channel, 1:2 Demux Mode (1:1 Demux Mode has similar performance), unless otherwise stated. INL vs. CODE DNL vs. CODE POWER CONSUMPTION vs. CLOCK FREQUENCY 1.9V 1000 MHz CLK ...
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ENOB vs. DIE TEMPERATURE ENOB vs. CLOCK FREQUENCY SNR vs. AMBIENT TEMPERATURE www.national.com ENOB vs. SUPPLY VOLTAGE 20206291 ENOB vs. INPUT FREQUENCY 20206278 SNR vs. DIE TEMPERATURE 20206268 22 20206277 20206279 20206293 ...
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SNR vs. SUPPLY VOLTAGE 20206269 SNR vs. INPUT FREQUENCY 20206271 THD vs. DIE TEMPERATURE 20206294 SNR vs. CLOCK FREQUENCY THD vs. AMBIENT TEMPERATURE THD vs. SUPPLY VOLTAGE 23 20206270 20206272 20206273 www.national.com ...
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THD vs. CLOCK FREQUENCY SFDR vs. AMBIENT TEMPERATURE SFDR vs. SUPPLY VOLTAGE www.national.com THD vs. INPUT FREQUENCY 20206274 SFDR vs. DIE TEMPERATURE 20206285 SFDR vs. CLOCK FREQUENCY 20206284 24 20206275 20206292 20206282 ...
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SFDR vs. INPUT FREQUENCY SIGNAL GAIN vs. INPUT FREQUENCY SPECTRAL RESPONSE 248 MHz IN GAIN STABILITY vs. DIE TEMPERATURE 20206283 CROSSTALK vs. SOURCE FREQUENCY 20206298 SPECTRAL RESPONSE AT f 20206287 25 20206295 20206263 = 498 MHz IN ...
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Functional Description The ADC08D1020 is a versatile A/D Converter with an inno- vative architecture permitting very high speed operation. The controls available ease the application of the device to circuit solutions. Optimum performance requires adherence to the provisions discussed ...
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The Analog Inputs The ADC08D1020 must be driven with a differential input sig- nal. Operation with a single-ended signal is not recommend- ed important that the inputs either be a.c. coupled to the inputs with the V ...
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TABLE 2. Input Channel Samples Produced at Data Outputs in Non-Demultiplexed Mode Data Outputs (Sourced with respect to fall of DCLK+) DI "I" Input Sampled with Fall of CLK 13 cycles earlier. DId No output. DQ "Q" Input Sampled with ...
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NORMAL/EXTENDED CONTROL The ADC08D1020 may be operated in one of two modes. In the simpler standard control mode, the user affects available configuration and control of the device through several control pins. The "extended control mode" provides additional con- ...
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The default state of the Extended Control Mode is set upon power-on reset (internally performed by the device) and is shown in Table 4. TABLE 4. Extended Control Mode Operation (Pin 41 Logic Low or Pin 14 Floating) Feature SDR ...
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REGISTER DESCRIPTION Nine write-only registers provide several control and config- uration options in the Extended Control Mode. These regis- ters have no effect when the device is in the Normal Control Mode. Each register description below also shows the ...
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I-Channel Offset Addr: 2h (0010b) D15 D14 D13 D12 D11 (MSB) Offset Value Sign Bits 15:8 Offset Value. The input offset of the I- Channel ADC is adjusted linearly and monotonically ...
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Q-Channel Full-Scale Voltage Adjust Addr: Bh (1011b) Write only (0x807F) D15 D14 D13 D12 D11 D10 (MSB) Adjust Value (LSB Bits 15:7 Full Scale Voltage Adjust Value. The input ...
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CLK input rising edge. The du- ration of the DCLK_RST pulse affects the length of time that the digital output will take before providing ...
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Applications Information 2.1 THE REFERENCE VOLTAGE The voltage reference for the ADC08D1020 is derived from a 1.254V bandgap reference, a buffered version of which is made available at pin 31 for user convenience. BG This output has ...
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FIGURE 13. Single-Ended to Differential Signal Conversion Using a Balun Figure generic depiction of a single-ended to differen- tial signal conversion using a balun. The circuitry specific to the balun will depend upon the type of balun ...
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Out Of Range (OR) Indication When the conversion result is clipped the Out of Range output is activated such that OR+ goes high and OR- goes low. This output is active as long as accurate data on either or ...
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Resistor Trim Disable is active. 2.4.2.1 Power-On Calibration Power-on calibration begins after a time delay following the application of power. This time delay is determined by the setting of CalDly, ...
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If the PD input is brought high while a calibration is running, the device will not go into power down until the calibration sequence is complete. However, if power is applied and PD is already high, the device will not ...
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This is not a problem if the ambient temperature is kept to a maximum of +85°C as specified in the Operating Ratings section. Please note that the following are general recommendations for mounting exposed pad devices onto a ...
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Best dynamic performance is obtained when the exposed pad at the back of the package has a good connection to ground. This is because this path from the ...
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Physical Dimensions NOTES: UNLESS OTHERWISE SPECIFIED REFERENCE JEDEC REGISTRATION MS-026, VARIATION BFB. 128-Lead, Exposed Pad, Low Profile, Quad, Flatpack (LQFP) www.national.com inches (millimeters) unless otherwise noted Order Number ADC08D1020CIYB NS Package Number VNX128A 42 ...
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Notes 43 www.national.com ...
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