ADC08D1020DEV/NOPB National Semiconductor, ADC08D1020DEV/NOPB Datasheet - Page 7

• Manufacturer Part Number: ADC08D1020DEV/NOPB
• Description: BOARD DEV FOR ADC08D1020
• Manufacturer: National Semiconductor
• Series: PowerWise®r

Specifications of ADC08D1020DEV/NOPB

• Number Of Adc's: 2
• Number Of Bits: 8
• Sampling Rate (per Second): 1G
• Data Interface: Serial
• Inputs Per Adc: 1 Differential
• Input Range: 870 mVpp
• Power (typ) @ Conditions: 1.6W @ 1GSPS
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: ADC08D1020
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ADC08D1020DEV

Pin Functions
100 / 61
101 / 60
102 / 59
103 / 58
104 / 57
105 / 56
106 / 55
107 / 54
111 / 50
112 / 49
113 / 48
114 / 47
115 / 46
116 / 45
117 / 44
118 / 43
122 / 39
123 / 38
124 / 37
125 / 36
Pin No.
83 / 78
84 / 77
85 / 76
86 / 75
89 / 72
90 / 71
91 / 70
92 / 69
93 / 68
94 / 67
95 / 66
96 / 65
79
80
82
81
DId7− / DQd7−
DId7+ / DQd7+
DId6− / DQd6−
DId6+ / DQd6+
DId5− / DQd5−
DId5+ / DQd5+
DId4− / DQd4−
DId4+ / DQd4+
DId3− / DQd3−
DId3+ / DQd3+
DId2− / DQd2−
DId2+ / DQd2+
DId1− / DQd1−
DId1+ / DQd1+
DId0− / DQd0−
DId0+ / DQd0+
OR+/DCLK2+
DI7− / DQ7−
DI7+ / DQ7+
DI6− / DQ6−
DI6+ / DQ6+
DI5− / DQ5−
DI5+ / DQ5+
DI4− / DQ4−
DI4+ / DQ4+
DI3− / DQ3−
DI3+ / DQ3+
DI2− / DQ2−
DI2+ / DQ2+
DI1− / DQ1−
DI1+ / DQ1+
DI0− / DQ0−
DI0+ / DQ0+
OR-/DCLK2-
Symbol
DCLK+
DCLK-
Equivalent Circuit
7
I and Q channel LVDS Data Outputs that are not delayed in
the output demultiplexer. Compared with the DId and DQd
outputs, these outputs represent the later time samples.
These outputs should always be terminated with a 100 Ω
differential resistor.
I and Q channel LVDS Data Outputs that are delayed by one
CLK cycle in the output demultiplexer. Compared with the
DI/DQ outputs, these outputs represent the earlier time
sample. These outputs should be terminated with a 100 Ω
differential resistor when enabled. In non-demultiplexed
mode, these outputs are disabled and are high impedance
when enabled. When disabled, these outputs must be left
floating.
Out Of Range output. A differential high at these pins
indicates that the differential input is out of range (outside the
range ±V
extended control mode or the Input Full-Scale Voltage Adjust
register setting in the extended control mode). DCLK2 is the
exact mirror of DCLK and should output the same signal at
the same rate.
Data Clock. Differential Clock outputs used to latch the
output data. Delayed and non-delayed data outputs are
supplied synchronous to this signal. In 1:2 demultiplexed
mode, this signal is at 1/2 the input clock rate in SDR mode
and at 1/4 the input clock rate in the DDR mode. By default,
the DCLK outputs are not active during the termination
resistor trim section of the calibration cycle. If a system
requires DCLK to run continuously during a calibration cycle,
the termination resistor trim portion of the cycle can be
disabled by setting the Resistor Trim Disable (RTD) bit to
logic high in the Extended Configuration Register (address
9h). This disables all subsequent termination resistor trims
after the initial trim which occurs during the power on
calibration. Therefore, this output is not recommended as a
system clock unless the resistor trim is disabled. When the
device is in the non-demultiplexed mode, DCLK can only be
in DDR mode and the signal is at 1/2 the input clock rate.
IN
/2 as programmed by the FSR pin in non-
Description
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