ADC08D1020DEV/NOPB National Semiconductor, ADC08D1020DEV/NOPB Datasheet - Page 33

• Manufacturer Part Number: ADC08D1020DEV/NOPB
• Description: BOARD DEV FOR ADC08D1020
• Manufacturer: National Semiconductor
• Series: PowerWise®r

Specifications of ADC08D1020DEV/NOPB

• Number Of Adc's: 2
• Number Of Bits: 8
• Sampling Rate (per Second): 1G
• Data Interface: Serial
• Inputs Per Adc: 1 Differential
• Input Range: 870 mVpp
• Power (typ) @ Conditions: 1.6W @ 1GSPS
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: ADC08D1020
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ADC08D1020DEV

Bits 15:7
Bits 6:0
Bits 15:8
Bits 7:0
(MSB)
Addr: Bh (1011b)
Addr: 1110
Addr: Fh (1111b)
(LSB)
(MSB)
(LSB)
POL
D15
D15
D15
Sample Clock Phase Intermediate/Coarse Adjust
D7
D7
D7
1
Q-Channel Full-Scale Voltage Adjust
D14
D6
D14
D14
1
D6
Sample Clock Phase Fine Adjust
D6
1
1
Full Scale Voltage Adjust Value. The input
full-scale voltage or gain of the I-Channel
ADC is adjusted linearly and monotonically
with a 9 bit data value. The adjustment range
is ±20% of the nominal 700 mV
value.
0000 0000 0
1000 0000 0
1111 1111 1
For best performance, it is recommended
that the value in this field be limited to the
range of 0110 0000 0b to 1110 0000 0b. i.e.,
limit the amount of adjustment to ±15%. The
remaining ±5% headroom allows for the
ADC's own full scale variation. A gain
adjustment does not require ADC re-
calibration.
POR State: 1000 0000 0b (no adjustment)
Must be set to 1b
Fine Phase Adjust. The phase of the ADC
sampling clock is adjusted monotonically by
the value in this field. 00h provides a nominal
zero phase adjustment, while FFh provides a
nominal 50 ps of delay. Thus, each code step
provides approximately 0.2 ps of delay.
POR State: 0000 0000b
Must be set to 1b
(MSB) Coarse Phase Adjust
D13
D5
D13
D13
1
D5
D5
1
1
Fine Phase Adjust
D12
D4
D12
1
D12
D4
D4
1
1
Adjust Value
D11
D3
D11
D11
1
D3
D3
1
1
560 mV
700 mV
840 mV
Write only (0x00FF)
Write only (0x807F)
Write only (0x007F)
D10
D2
D10
D10
1
D2
D2
1
1
P-P
P-P
P-P
P-P
D9
D1
1
D9
D1
differential
D9
D1
1
1
IPA
(LSB)
D8
D0
1
D8
D0
D8
D0
1
1
33
1.4.1 Note Regarding Clock Phase Adjust
This is a feature intended to help the system designer remove
small imbalances in clock distribution traces at the board level
when multiple ADCs are used. Please note, however, that
enabling this feature will reduce the dynamic performance
(ENOB, SNR, SFDR) some finite amount. The amount of
degradation increases with the amount of adjustment applied.
The user is strongly advised to (a) use the minimal amount of
adjustment; and (b) verify the net benefit of this feature in his
system before relying on it.
1.4.2 Note Regarding Extended Mode Offset Correction
When using the I or Q channel Offset Adjust registers, the
following information should be noted.
For offset values of +0000 0000 and −0000 0000, the actual
offset is not the same. By changing only the sign bit in this
case, an offset step in the digital output code of about 1/10th
of an LSB is experienced. This is shown more clearly in the
Figure below.
1.5 MULTIPLE ADC SYNCHRONIZATION
The ADC08D1020 has the capability to precisely reset its
sampling clock input to DCLK output relationship as deter-
mined by the user-supplied DCLK_RST pulse. This allows
multiple ADCs in a system to have their DCLK (and data) out-
puts transition at the same time with respect to the shared
CLK input that all the ADCs use for sampling.
The DCLK_RST signal must observe some timing require-
ments that are shown in
Timing Diagrams. The DCLK_RST pulse must be of a mini-
Bit 15
Bits 14:10 Coarse Phase Adjust. Each code value in
Bits 9:7
Bits 6:0
FIGURE 11. Extended Mode Offset Behavior
Polarity Select. When this bit is selected, the
polarity of the ADC sampling clock is
inverted.
POR State: 0b
this field delays the sample clock by
approximately 65 ps. A value of 00000b in
this field causes zero adjustment.
POR State: 00000b
Intermediate Phase Adjust. Each code value
in this field delays the sample clock by
approximately 11 ps. A value of 000b in this
field causes zero adjustment. Maximum
combined adjustment using Coarse Phase
Adjust and Intermediate Phase adjust is
approximately 2.1ns.
POR State: 000b
Must be set to 1b
Figure
7,
Figure 8
and
Figure 9
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