ADC08D1020DEV/NOPB National Semiconductor, ADC08D1020DEV/NOPB Datasheet - Page 34

• Manufacturer Part Number: ADC08D1020DEV/NOPB
• Description: BOARD DEV FOR ADC08D1020
• Manufacturer: National Semiconductor
• Series: PowerWise®r

Specifications of ADC08D1020DEV/NOPB

• Number Of Adc's: 2
• Number Of Bits: 8
• Sampling Rate (per Second): 1G
• Data Interface: Serial
• Inputs Per Adc: 1 Differential
• Input Range: 870 mVpp
• Power (typ) @ Conditions: 1.6W @ 1GSPS
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: ADC08D1020
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ADC08D1020DEV

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mum width and its deassertion edge must observe setup and
hold times with respect to the CLK input rising edge. The du-
ration of the DCLK_RST pulse affects the length of time that
the digital output will take before providing valid data again
after the end of the reset condition. Therefore, the DCLK_RST
pulse width should be made reasonably short within the sys-
tem application constraints. These timing specifications are
listed as t
acteristics.
The DCLK_RST signal can be asserted asynchronous to the
input clock. If DCLK_RST is asserted, the DCLK output is held
in a designated state. The state in which DCLK is held during
the reset period is determined by the mode of operation (SDR/
DDR) and the setting of the Output Edge configuration pin or
bit. (Refer to
reset state conditions). Therefore, depending upon when the
DCLK_RST signal is asserted, there may be a narrow pulse
on the DCLK line during this reset event. When the
DCLK_RST signal is de-asserted in synchronization with the
CLK rising edge, there are three or four CLK cycles of sys-
tematic delay and the next CLK falling edge synchronizes the
DCLK output with those of other ADC08D1020s in the sys-
tem. The DCLK output is enabled again after a constant delay
(relative to the input clock frequency) which is equal to the
CLK input to DCLK output delay (t
hibits this delay characteristic in normal operation. The user
has the option of using a single-ended DCLK_RST signal, but
a differential DCLK_RST is strongly recommended due to its
superior timing specifications.
As shown in
Diagrams, there is a delay from the deassertion of
DCLK_RST to the reappearance of DCLK, which is equal to
several cycles of CLK plus t
DCLK_RST is not latched in until the next falling edge of CLK.
For 1:2 Demux DDR 0° Mode, there are four CLK cycles of
delay; for all other modes, there are three CLK cycles of delay.
If the device is not programmed to allow DCLK to run contin-
uously, DCLK will become inactive during a calibration cycle.
Therefore, it is strongly recommended that DCLK only be
used as a data capture clock and not as a system clock.
The DCLK_RST pin should NOT be brought high while the
calibration process is running (while CalRun is high). Doing
so could cause a digital glitch in the digital circuitry, resulting
in corruption and invalidation of the calibration.
1.6 ADC TEST PATTERN
To aid in system debug, the ADC08D1020 has the capability
of providing a test pattern at the four output ports completely
independent of the input signal. The ADC is disengaged and
a test pattern generator is connected to the outputs including
OR. The test pattern output is the same in DES mode and
non-DES mode. Each port is given a unique 8-bit word, alter-
nating between 1's and 0's as described in
7.
Time
T0
T1
T2
T3
T4
TABLE 6. Test Pattern by Output Port in
RH
FEh
FEh
01h
01h
01h
Qd
, t
Figure
Figure
RS
, and t
1:2 Demultiplex Mode
FDh
FDh
02h
02h
02h
Id
7,
7,
PWR
Figure
Figure 8
FCh
FCh
03h
03h
03h
in the Converter Electrical Char-
Q
OD
8, and
. Note that the deassertion of
and
FBh
FBh
OD
04h
04h
04h
I
). The device always ex-
Figure 9
Figure 9
OR
0
1
0
1
0
Table 6
for the DCLK
of the Timing
Comments
Sequence
Pattern
and
n
Table
34
With the part programmed into the non-demultiplex mode, the
test pattern’s order will be as described in
It is possible for the I and the Q channels' test patterns to be
not synchronized. Either I and Id or Q and Qd patterns may
be slipped by one DCLK.
To ensure that the test pattern starts synchronously in each
port, set DCLK_RST while writing the Test Pattern Output bit
in the Extended Configuration Register. The pattern appears
at the data output ports when DCLK_RST is cleared low. The
test pattern will work at speed and will work with the device in
the SDR, DDR and the non-demultiplex output modes.
Time
T10
T11
T5
T6
T7
T8
T9
Time
T10
T11
T12
T13
T14
T15
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
TABLE 7. Test Pattern by Output Port in
FEh
FEh
01h
01h
01h
01h
Qd
...
FEh
FEh
FEh
FEh
FEh
FEh
01h
01h
01h
01h
01h
01h
01h
01h
01h
...
Q
Non-demultiplex Mode
FDh
FDh
02h
02h
02h
02h
Id
...
FDh
FDh
FDh
FDh
FDh
FDh
02h
02h
02h
02h
02h
02h
02h
02h
02h
...
I
FCh
FCh
03h
03h
03h
03h
Q
...
FBh
FBh
04h
04h
04h
04h
OR
...
...
I
0
1
0
0
1
1
0
0
1
0
0
1
0
0
1
OR
...
0
1
0
1
0
0
Table
Comments
Sequence
Sequence
Sequence n
Comments
Pattern
Pattern
Sequence
7.
n+1
Pattern
Pattern
n
n+1
+2