LM20333EVAL National Semiconductor, LM20333EVAL Datasheet - Page 10

• Manufacturer Part Number: LM20333EVAL
• Description: EVALUATION BOARD FOR THE LM20333
• Manufacturer: National Semiconductor
• Series: PowerWise®r

Specifications of LM20333EVAL

• Main Purpose: DC/DC, Step Down
• Outputs And Type: 1, Non-Isolated
• Voltage - Output: 3.3V
• Current - Output: 3A
• Voltage - Input: 4.5 ~ 25V
• Regulator Topology: Buck
• Board Type: Fully Populated
• Utilized Ic / Part: LM20333
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Power - Output: -
• Frequency - Switching: -

www.national.com
Operation Description
GENERAL
The LM20333 switching regulator features all of the functions
necessary to implement an efficient buck regulator using a
minimum number of external components. This easy to use
regulator features two integrated switches and is capable of
supplying up to 3A of continuous output current. The regulator
utilizes peak current mode control with nonlinear slope com-
pensation to optimize stability and transient response over the
entire output voltage range. Peak current mode control also
provides inherent line feed-forward, cycle-by-cycle current
limiting and easy loop compensation. The switching frequen-
cy can be synchronized to an external oscillator over the
range of 250 kHz to 1.5 MHz. The SYNC function allows the
device to operate at high switching frequencies minimizing
the size of the inductor while still achieving efficiencies as high
as 94%. The precision internal voltage reference allows the
output to be set as low as 0.8V. Fault protection features in-
clude: current limiting, thermal shutdown, over voltage pro-
tection, and shutdown capability. The device is available in
the eTSSOP-20 package featuring an exposed pad to aid
thermal dissipation. The typical application circuit for the
LM20333 is shown in Figure 1 in the design guide.
PRECISION ENABLE
The enable (EN) pin allows the output of the device to be en-
abled or disabled with an external control signal. This pin is a
precision analog input that enables the device when the volt-
age exceeds 1.25V (typical). The EN pin has 50 mV of hys-
teresis and will disable the output when the enable voltage
falls below 1.2V (typical). If the EN pin is not used, it should
be disconnected so the internal 2 µA pull-up will default this
function to the enabled condition. Since the enable pin has a
precise turn-on threshold it can be used along with an external
resistor divider network from V
turn-on at a precise input voltage. The precision enable cir-
cuitry will remain active even when the device is disabled.
FREQUENCY SYNCHRONIZATION
The frequency sychronization pin(SYNC) allows the switching
frequency of the device to be controlled with an external clock
signal. This feature allows the user to sychronize multiple
converters, avoiding undesirable frequency bands of opera-
tion.
The switching frequency of the device will synchronize to the
rising edge of the clock source that is driving the SYNC pin.
The logic low level for the input clock must be below 0.8V and
the logic high level must exceed 2.0V to guarantee proper
operation. The device will synchronize to frequencies from
250 kHz to 1.5 MHz. If the synchronization clock is removed
or not present during startup, the oscillator of the device will
run at approximately 200 kHz. If the SYNC pin is not used it
should be connected to ground.
PEAK CURRENT MODE CONTROL
In most cases, the peak current mode control architecture
used in the LM20333 only requires two external components
to achieve a stable design. The compensation can be select-
ed to accommodate any capacitor type or value. The external
compensation also allows the user to set the crossover fre-
quency and optimize the transient performance of the device.
For duty cycles above 50% all peak current mode control buck
converters require the addition of an artificial ramp to avoid
sub-harmonic oscillation. This artificial linear ramp is com-
monly referred to as slope compensation. What makes the
IN
to configure the device to
10
LM20333 unique is the amount of slope compensation will
change depending on the output voltage. When operating at
high output voltages the device will have more slope com-
pensation than when operating at lower output voltages. This
is accomplished in the LM20333 by using a non-linear
parabolic ramp for the slope compensation. The parabolic
slope compensation of the LM20333 is an improvement over
the traditional linear slope compensation because it optimizes
the stability of the device over the entire output voltage range.
CURRENT LIMIT
The precise current limit enables the device to operate with
smaller inductors that have lower saturation currents. When
the peak inductor current reaches the current limit threshold,
an over current event is triggered and the internal high-side
FET turns off and the low-side FET turns on, allowing the in-
ductor current to ramp down until the next switching cycle. For
each sequential over-current event, the reference voltage is
decremented and PWM pulses are skipped resulting in a cur-
rent limit that does not aggressively fold back for brief over-
current events, while at the same time providing frequency
and voltage foldback protection during hard short circuit con-
ditions.
SOFT-START AND VOLTAGE TRACKING
The SS/TRK pin is a dual function pin that can be used to set
the startup time or track an external voltage source. The start-
up or soft-start time can be adjusted by connecting a capacitor
from the SS/TRK pin to ground. The soft-start feature allows
the regulator output to gradually reach the steady state oper-
ating point, thus reducing stresses on the input supply and
controlling startup current. If no soft-start capacitor is used the
device defaults to the internal soft-start circuitry resulting in a
startup time of approximately 1 ms. For applications that re-
quire a monotonic startup or utilize the PGOOD pin, an ex-
ternal soft-start capacitor is recommended. The SS/TRK pin
can also be set to track an external voltage source. The track-
ing behavior can be adjusted by two external resistors con-
nected to the SS/TRK pin as shown in Figure 6 in the design
guide.
PRE-BIAS STARTUP CAPABILITY
The LM20333 is in a pre-biased state when it starts up with
an output voltage greater than zero. This often occurs in many
multi-rail applications such as when powering an FPGA,
ASIC, or DSP. In these applications the output can be pre-
biased through parasitic conduction paths from one supply
rail to another. Even though the LM20333 is a synchronous
converter, it will not pull the output low when a pre-bias con-
dition exists. During start up the LM20333 will not sink current
until the soft-start voltage exceeds the voltage on the FB pin.
Since the device cannot sink current, it protects the load from
damage that might otherwise occur if current is conducted
through the parasitic paths of the load.
POWER GOOD AND OVER VOLTAGE FAULT HANDLING
The LM20333 has built in under and over voltage compara-
tors that control the power switches. Whenever there is an
excursion in output voltage above the set OVP threshold, the
part will terminate the present on-pulse, turn-on the low-side
FET, and pull the PGOOD pin low. The low-side FET will re-
main on until either the FB voltage falls back into regulation
or the negative current limit is triggered which in turn tri-states
the FETs. If the output reaches the UVP threshold the part will
continue switching and the PGOOD pin will be deasserted
and go low. Typical values for the PGOOD resistor are on the
order of 100 kΩ or less. To avoid false tripping during transient