LM2647EVAL National Semiconductor, LM2647EVAL Datasheet - Page 14

• Manufacturer Part Number: LM2647EVAL
• Description: BOARD EVALUATION LM2647
• Manufacturer: National Semiconductor

Specifications of LM2647EVAL

• Main Purpose: DC/DC, Step Down
• Outputs And Type: 2, Non-Isolated
• Voltage - Output: 3.3V, 5V
• Current - Output: 2A, 2A
• Voltage - Input: 5.5 ~ 28V
• Regulator Topology: Buck
• Board Type: Fully Populated
• Utilized Ic / Part: LM2647
• Lead Free Status / RoHS Status: Not applicable / Not applicable
• Power - Output: -
• Frequency - Switching: -

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Operation Descriptions
CH1: PGOOD, CH2: VIN, CH3: LDRV, CH4: Vo
Output 1V
660µF
The recovery procedure from a VIN Power-off is the same as
for any fault condition.
VDD POWER-OFF (UVLO)
Whenever VDD starts to fall, and drops below about 4V,
LDRV goes high immediately, ‘Power Not Good’ is signaled
and in effect a fault condition (in this case an Under-voltage
lockout) is asserted. Recovery from a fault is discussed next.
FAULT AND RECOVERY
If any output falls outside the Power Good window, the
response is a ‘Power Not Good’ signal. The FET drive sig-
nals are not affected. But under a fault condition assertion,
LDRV goes high immediately turning the low side FETs ON
and discharging the output capacitors. Note that the current
will then invariably slew momentarily negative (passing from
Drain to Source of lower FETs), before it settles down to
zero.
A fault will be detected when either output falls below the
Under-voltage threshold, or rises above the Over-voltage
threshold. From its detection to assertion, there is a 7µs
delay to help prevent spurious responses.
A fault condition is also asserted during a loss of the VIN rail
or the VDD rail, though not if shutdown is achieved by use of
the Enable pin.
To recover from a fault, either of the following options is
available:
@
FIGURE 8. VIN Removal in SKIP Mode
0.02A, VIN = 9.75V, SKIP, L = 10µH, f = 300kHz, C
(Continued)
OUT
20056316
=
14
a) Enable pin is toggled: i.e. taken low (below 0.8V), then
high again (2V to 5V). This must be done with VDD between
4.5V to 5V and VIN within normal range (5.5V to 28V).
b) VDD is brought below 1.0V and then brought back up
between 4.5V to 5V. This must be done with the Enable pin
held high (2V to 5V) and VIN within normal range (5.5V to
28V).
Recovery will initiate a Soft-start sequence (see description
under section ‘Soft-start’ above).
CURRENT LIMIT AND PROTECTION
Output current limiting is achieved by sensing the negative
Vds drop across the low side FET when the FET is turned
on. The Current Limit Comparator (see Block Diagram)
monitors the voltage at the ILIM pin with 62µA (typical value)
of current being sourced from the pin. The 62µA source flows
through an external resistor connected between ILIM and
the Drain of the lower FET. The voltage drop across the ILIM
resistor is compared with the drop across the lower FET and
the current limit comparator trips when the two are of the
same magnitude. This determines the threshold of current
limiting. For example, if excessive inductor current causes
the voltage across the lower FET to exceed the voltage drop
across the ILIM resistor, the ILIM pin will go negative (with
respect to ground) and trip the comparator. The comparator
then sets a latch which prevents the top FET from turning
ON during the next PWM clock cycle. The top FET will
resume switching only if the current limit comparator was not
tripped in the previous switching cycle.
The Soft-start capacitor at the SS pin is discharged with a
115µA current source when an overcurrent event is in
progress. Therefore if the overcurrent condition does not last
long enough to cause a fault assertion, the Soft-start capaci-
tor will charge back up (by I
teristics table), without any user intervention. The purpose of
discharging the Soft-start capacitor during an overcurrent
event is to eventually allow the voltage on the SS pin to fall
low enough to cause additional duty cycle limiting (over and
above the protection provided by the adaptive duty cycle
clamp). Note that once the duty cycle starts pinching-off as a
result of the progressive reduction in SS pin voltage, the
output voltage will certainly start collapsing (if it hasn’t done
so already), and this will hasten a fault condition assertion
(an Under-voltage in this case). Thereafter, a normal fault-
recovery sequence will have to be initiated to cause the
outputs to return to regulation.
There is a race condition in effect, between the current limit
being reached and a fault being asserted (Under-voltage). It
could happen that if the load current was very low before the
sudden overload was applied, a fault condition could be
asserted even before the current limit has been reached.
See the differences between Figure 9 and Figure 10 to see
the possibilities. Also see ‘Application Information’ for a
deeper understanding of current limiting discussed at a
quantitative level.
SS_CHG
, see Electrical Charac-