LM2647EVAL National Semiconductor, LM2647EVAL Datasheet - Page 3

• Manufacturer Part Number: LM2647EVAL
• Description: BOARD EVALUATION LM2647
• Manufacturer: National Semiconductor

Specifications of LM2647EVAL

• Main Purpose: DC/DC, Step Down
• Outputs And Type: 2, Non-Isolated
• Voltage - Output: 3.3V, 5V
• Current - Output: 2A, 2A
• Voltage - Input: 5.5 ~ 28V
• Regulator Topology: Buck
• Board Type: Fully Populated
• Utilized Ic / Part: LM2647
• Lead Free Status / RoHS Status: Not applicable / Not applicable
• Power - Output: -
• Frequency - Switching: -

Pin Description
output capacitors. The voltage on this pin finally clamps
close to 5V. This pin is again connected to the internal 115µA
current sink whenever a current limit event is in progress.
This sink current discharges the Soft-start capacitor and
forces the duty cycle low to protect the power components.
When a fault condition is asserted (See Pin 2) the SS pin is
internally connected to ground via the 1.8 kΩ resistor.
Pin 5, VDD: 5V supply rail for the control and logic sections
of both channels. For normal operation to start, the voltage
on this pin must be brought above 4.5V. Subsequently, the
voltage on this pin (including any ripple component) should
not allowed to fall below 4V for a duration longer than 7µs.
Since this pin is also the supply rail for the internal control
sections, it should be well-decoupled particularly at high
frequencies. A minimum 0.1µF-0.47µF (ceramic) capacitor
should be placed on the component side very close to the IC
with no intervening vias between this capacitor and the
VDD/SGND pins. If the voltage on Pin 5 falls below the lower
UVLO threshold, both upper FETs are latched OFF and
lower FETs latched ON. Power Not Good is then also sig-
naled immediately (on Pin 9). To effect recovery, the EN pin
must be taken below 0.8V and then back above 2V (with
VDD held above 4.5V). Or the voltage on the VDD pin must
be taken below 1.0V and then back again above 4.5V (with
EN pin held above 2V). Normal operation will then resume
assuming that the fault condition has cleared.
Pin 6, FREQ: Frequency adjust pin. The switching frequency
(for both channels) is set by a resistor connected between
this pin and ground. A value of 22.1kΩ sets the frequency to
300kHz (nominal). If the resistance is increased, the switch-
ing frequency falls. An approximate relationship is that for
every 7.3kΩ increase (or decrease) in the value of the fre-
quency adjust resistance, the time period (1/f) increases (or
decreases) by about 1µs.
Pin 7, SGND: Signal Ground pin. This is the lower rail for the
control and logic sections of both channels. SGND should be
connected on the PCB to the system ground, which in turn is
connected to PGND1 and PGND2. The layout is important
and the recommendations in the section Layout Guidelines
should be followed.
Pin 8, EN: IC Enable pin. When EN is taken high, both
channels are enabled by means of a Soft-start power-up
sequence (see Pin 4). When EN is brought low, Power Not
Good is signaled within 100ns. This causes Soft-shutdown to
occur (see Pins 1 and 9). The Soft-start capacitor is then
discharged by an internal 1.8kΩ resistor (R
Electrical Characteristics table). But note that when the En-
able pin is toggled, a fault condition is not asserted. There-
fore in this case, the lower FETs are not latched ON, even as
the output voltage ramps down, eventually falling below the
under-voltage threshold. In fact, in this situation, both the
upper and the lower FETs of the two channels are latched
OFF, until the Enable pin is taken high again. If a fault
shutdown has occurred, taking the Enable pin low and then
high again (toggling), resets the internal latches, and the IC
will resume normal switching operation.
Pin 9, PGOOD: Power Good output pin. An open-Drain logic
output that is pulled high with an external pull-up resistor,
indicating that both output voltages are within a pre-defined
Power Good window. Outside this window, the pin is inter-
nally pulled low (Power Not Good signaled) provided the
output error lasts for more than 7µs. But the pin is also pulled
low within 100ns of the Enable pin being taken low, irrespec-
tive of the output voltage level. Note that PGOOD must
(Continued)
SS_DCHG
, see
3
always be high before it can respond by going low. So
regulation on both channels must be achieved first. Further,
for fault monitoring to be in place, PGOOD must have been
high prior to occurrence of the fault condition. Note that since
under a fault assertion, the lower FETs are always latched
ON, this will not happen if regulation has not been already
been achieved first. For correct signaling on this pin under
single-channel operation, see description of Pin 2.
Pin 10, FPWM: Logic input for selecting either the Forced
PWM (FPWM) Mode or Pulse-skip Mode (SKIP) for both
channels (together). When the pin is driven high, the IC
operates in the FPWM mode, and when pulled low or left
floating, the SKIP mode is enabled. In FPWM mode, the
lower FET of a given channel is always ON whenever the
upper FET is OFF (except for a narrow shoot-through pro-
tection deadband). This leads to continuous conduction
mode of operation, which has a fixed frequency and (almost)
fixed duty cycle down to very light loads. But this does
reduce efficiency at light loads. The alternative is the SKIP
mode, where the lower FET remains ON only until the volt-
age on the Switch pin (see Pin 27 or Pin 16) is more negative
than 2.2mV (typical). So for example, for a 21mΩ FET, this
translates to a current threshold of 2.2mV/21mΩ = 0.1A.
Therefore, if the (instantaneous) inductor current falls below
this value, the lower FET will turn OFF every cycle at this
point (when operated in SKIP mode). This threshold is set by
the zero-cross Comparator in the Block Diagram. Note that if
the inductor current waveform is high enough to be always
above this zero-cross threshold (V
Electrical Characteristics), there will be no observable differ-
ence between FPWM and SKIP mode settings (in steady-
state). SKIP mode, when it actually occurs, is clearly a
discontinuous mode of operation. However, note that in con-
ventional discontinuous mode, the duty cycle keeps falling
(towards zero) as the load decreases. But the LM2647 does
not allow the duty cycle to fall by more than 15% of its
original value (at the CCM-DCM boundary). This forces
pulse-skipping, and the average frequency is effectively de-
creased as the load decreases. This mode of operation
improves efficiency at light loads, but the frequency is effec-
tively no longer a constant. Note that a minimum pre-load of
0.1mA should be maintained on the output of each channel
to ensure regulation in SKIP mode. The resistive divider from
output to ground used to set the output voltage could be
designed to serve as part or all of this required pre-load.
Pin 11, SS2: Soft-start pin for Channel 2. See Pin 4.
Pin 12, COMP2: Soft-start pin for Channel 2. See Pin 3.
Pin 13, FB2: Feedback pin for Channel 2. See Pin 2.
Pin 14, SENSE2: Output voltage sense pin for Channel 2.
See Pin 1.
Pin 15, ILIM2: Channel 2 Current Limit pin. When the bottom
FET is ON, a 62µA (typical) current flows out of this pin into
an external current limit setting resistor connected to the
Drain of the lower FET. This is a current source, therefore the
drop across this resistor serves to push the voltage on this
pin to a more positive value. However, the Drain of the lower
FET which is connected to the other side of the same
resistor is trying to go more negative as the load current
increases. At some value of instantaneous current, the volt-
age on this pin will transit from positive to negative. The point
where it is zero is the current limiting condition and is de-
tected by the Current Limit Comparator in the Block Dia-
gram. When current limit condition has been detected, the
next ON-pulse of the upper FET will be omitted. The lower
FET will again be monitored to determine if the current has
fallen below the threshold. If it has, the next ON-pulse will be
SW_ZERO
, see Table of
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