LP5521TMEV National Semiconductor, LP5521TMEV Datasheet - Page 13

• Manufacturer Part Number: LP5521TMEV
• Description: EVAL BOARD FOR LP5521
• Manufacturer: National Semiconductor

Specifications of LP5521TMEV

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: Q5109809

Modes of Operation
RESET:
STANDBY:
STARTUP:
NORMAL:
POWER SAVE: In POWER SAVE mode analog blocks are disabled to minimize power consumption. See chapter Power Save
In the RESET mode all the internal registers are reset to the default values. Reset is done always if Reset Register
(0DH) is written FFH or internal Power On Reset is activated. Power On Reset (POR) will activate when supply
voltage is connected or when the supply voltage V
inactivate and the chip will continue to the STANDBY mode. CHIP_EN control bit is low after POR by default.
The STANDBY mode is entered if the register bit CHIP_EN or EN pin is LOW and Reset is not active. This is the
low power consumption mode, when all circuit functions are disabled. Registers can be written in this mode if
EN pin is high. Control bits are effective after start up.
When CHIP_EN bit is written high and EN pin is high, the INTERNAL STARTUP SEQUENCE powers up all the
needed internal blocks (V
the Thermal Shutdown (TSD) disables the chip operation and the chip state is in STARTUP mode, until no thermal
shutdown event is present.(Note 3)
During NORMAL mode the user controls the chip using the Control Registers. If EN pin is set low, the CHIP_EN
bit is reset to 0.
Mode for further information.
REF
, Bias, Oscillator etc.). Startup delay is 500 μs. If the chip temperature rises too high,
13
DD
falls below 1.5V. Once V
20186275
DD
rises above 1.5V, POR will
www.national.com