LP5521TMEV National Semiconductor, LP5521TMEV Datasheet - Page 32

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LP5521TMEV

Manufacturer Part Number
LP5521TMEV
Description
EVAL BOARD FOR LP5521
Manufacturer
National Semiconductor
Datasheets

Specifications of LP5521TMEV

Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
Q5109809
www.national.com
Operation Mode Register (OP MODE)
Address 01H
Reset value 00H
MODE registers are synchronized to 32 kHz clock. Delay between consecutive I
longer than 153 μs (typ).
R channel PWM control (R_PWM)
Address 02H
Reset value 00H
G Channel PWM Control (G_PWM)
Address 03H
Reset value 00H
G_PWM
G_MODE
R_PWM
R_MODE
B_MODE
Name
Name
Name
7
7
7
Bit
7:0
7:0
Bit
Bit
5:4
3:2
1:0
6
6
6
Access
R/W
Access
R/W
Access
R/W
R/W
R/W
R_MODE[1]
Active
5
5
5
Active
Active
G Channel PWM value during direct control operation mode
R_MODE[0]
Description
R Channel PWM value during direct control operation mode
OP Mode Register
R PWM Register
G PWM Register
4
4
4
Description
R channel operation mode
00b = Disabled
01b = Load program to SRAM, reset R channel PC
10b = Run program defined by R_EXEC
11b = Direct control
G channel operation mode
00b = Disabled
01b = Load program to SRAM, reset G channel PC
10b = Run program defined by G_EXEC
11b = Direct control
B channel operation mode
00b = Disabled
01b = Load program to SRAM, reset B channel PC
10b = Run program defined by B_EXEC
11b = Direct control
G_PWM[7:0]
R_PWM[7:0]
32
G_MODE[1]
3
3
3
2
C writes to OP_MODE register (01H) need to be
Description
G_MODE[0]
2
2
2
B_MODE[1]
1
1
1
B_MODE[0]
0
0
0

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