CY3218-CAPEXP1 Cypress Semiconductor Corp, CY3218-CAPEXP1 Datasheet
CY3218-CAPEXP1
Specifications of CY3218-CAPEXP1
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CY3218-CAPEXP1 Summary of contents
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... Nonvolatile storage of custom settings ❐ Easy integration into existing products – configure output to match system ❐ No external components required ❐ World class free configuration tool Cypress Semiconductor Corporation Document Number: 001-54606 Rev. *E CapSense ■ Wide range of operating voltages ❐ 2 2.9 V ❐ ...
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Contents Pinouts .............................................................................. 3 Typical Circuits ................................................................. 6 I2C Interface ...................................................................... 8 I2C Device Addressing ................................................ 8 I2C Clock Stretching .................................................... 8 Format for Register Write and Read ........................... 9 Operating Modes of I2C Commands ............................. 10 Normal Mode ............................................................. ...
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Pinouts [1, 2] Table 1. 16-pin QFN (no e-pad) Pin No. Pin Name 1 GP0[0] Configurable as CapSense or GPIO 2 GP0[1] Configurable as CapSense or GPIO SCL I C clock ...
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Table 2. 16-pin SOIC Pin No Name 1 GP0[3] Configurable as CapSense or GPIO 2 CSint Integrating capacitor input. The external capacitance is required only if 5:1 SNR cannot be achieved. Typical range ...
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Figure 3. Pin Diagram – 8-pin SOIC – CY8C20142 (4 Button) Table 3. Pin Definitions – 8-pin SOIC – CY8C20142 (4 Button) Pin No Name 1 V Ground SCL I C Clock 2 ...
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Typical Circuits Figure 4. Circuit 1 – Five Buttons and Five LEDs with I VDD_CE D1 VDD_CE R3 R4 4.7K 4. 330E R10 330E Figure 5. Circuit 2 – Two Buttons and Two LEDs with I ...
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Figure 6. Circuit 3 – Compatibility with 1 Note 1.8 V ≤ VDD_I2C ≤ VDD_CE and 2.4 V ≤ VDD_CE ≤ 5.25 V Figure 7. Circuit 4 – Powering Down CapSense Express Device for Low Power Requirements Output ...
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I C Interface The CapSense Express devices support the industry standard I ■ Configuring the device ■ Reading the status and data registers of the device ■ Controlling device operation ■ Executing commands 2 The I C address can ...
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Format for Register Write and Read Register write format Start Slave Addr + W A Reg Addr Register read format Start Slave Addr + W A Reg Addr Start Slave Addr + R A Data Legends: Master A - ACK ...
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Operating Modes Commands Normal Mode In normal mode of operation, the acknowledgment time is optimized. The timings remain approximately the same for different configurations of the slave. To reduce the acknowledgment times in normal mode, the ...
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LED Dimming Mode 1: Change Intensity on ON/OFF Button Status LED Dimming Mode 2: Flash Intensity on ON Button Status Document Number: 001-54606 Rev. *E CY8C20110, CY8C20180 CY8C20160, CY8C20140 CY8C20142 Page [+] Feedback ...
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LED Dimming Mode 3: Hold Intensity After ON/OFF Button Transition LED Dimming Mode 4: Toggle Intensity on ON/OFF or OFF/ON Button Transitions Note LED DIMMING is available only in CY8C20110. Document Number: 001-54606 Rev. *E CY8C20110, CY8C20180 CY8C20160, ...
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Register Map Register Name Address Access (in Hex) INPUT_PORT0 00 INPUT_PORT1 01 STATUS_POR0 02 STATUS_POR1 03 OUTPUT_PORT0 04 OUTPUT_PORT1 05 CS_ENABL0 06 CS_ENABLE 07 GPIO_ENABLE0 08 GPIO_ENABLE1 09 INVERSION_MASK0 0A INVERSION_MASK1 0B INT_MASK0 0C INT_MASK1 0D STATUS_HOLD_MSK0 0E STATUS_HOLD_MSK1 0F ...
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Register Map (continued) Register Name Address Access (in Hex) OPR2_PRT0_02 29 OPR2_PRT1_02 2A OP_SEL_03 2B OPR1_PRT0_03 2C OPR1_PRT1_03 2D OPR2_PRT0_03 2E OPR2_PRT1_03 2F OP_SEL_04 30 OPR1_PRT0_04 31 OPR1_PRT1_04 32 OPR2_PRT0_04 33 OPR2_PRT1_04 34 OP_SEL_10 35 OPR1_PRT0_10 36 OPR1_PRT1_10 37 OPR2_PRT0_10 ...
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Register Map (continued) Register Name Address Access (in Hex) CS_DEBOUNCE 53 CS_NEG_NOISE_TH 54 CS_LOW_BL_RST 55 CS_FILTERING 56 CS_SCAN_POS_00 57 CS_SCAN_POS_01 58 CS_SCAN_POS_02 59 CS_SCAN_POS_03 5A CS_SCAN_POS_04 5B CS_SCAN_POS_10 5C CS_SCAN_POS_11 5D CS_SCAN_POS_12 5E CS_SCAN_POS_13 5F CS_SCAN_POS_14 60 CS_FINGER_TH_00 61 CS_FINGER_TH_01 ...
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Register Map (continued) Register Name Address Access (in Hex) [18] 7D SLEEP_PIN 7E SLEEP_CTRL 7F SLEEP_SA_CNTR 80 CS_READ_BUTTON 81 CS_READ_BLM 82 CS_READ_BLL 83 CS_READ_DIFFM 84 CS_READ_DIFFL 85 CS_READ_RAWM 86 CS_READ_RAWL 87 CS_READ_STATUSM 88 CS_READ_STATUSL 89 [18] 8A [18] 8B [18] ...
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CapSense Express Commands [19] Command Description Get firmware revision Store current configuration to NVM Restore factory configuration Write NVM POR defaults ...
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Layout Guidelines and Best Practices CapSense Button Shapes Button Layout Design X: Button to ground clearance (Refer to Table 6 on page Y: Button to button clearance (Refer to Table 6 on page Recommended via Hole Placement Table 6. ...
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Table 6. Recommended Layout Guidelines and Best Practices (continued) Sl Category 9 Trace routing 10 Via position for the sensors 11 Via hole size for sensor traces 12 Number of vias on sensor trace 13 CapSense series resistor placement 14 ...
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Example PCB Layout Design with Two CapSense Buttons and Two LEDs Document Number: 001-54606 Rev. *E CY8C20110, CY8C20180 CY8C20160, CY8C20140 Figure 10. Top Layer Figure 11. Bottom Layer CY8C20142 Page [+] Feedback ...
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Operating Voltages 2 For details ACK time, refer to “Register Map” time is approximately four times the values mentioned in these tables. CapSense Constraints Parameter Parasitic capacitance ( the P CapSense sensor Overlay thickness ...
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Electrical Specifications Absolute Maximum Ratings Parameter Description T Storage temperature STG T Bake temperature BAKETEMP t Bake time BAKETIME T Ambient temperature with power A applied V Supply voltage on V relative input voltage ...
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DC Electrical Characteristics DC Chip Level Specifications Parameter Description V Supply voltage DD I Supply current DD ISB Deep sleep mode current with POR and LVD active ISB Deep sleep mode current with POR and LVD active ISB Deep sleep ...
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Table 8. 2.7-V DC GPIO Specifications Parameter Description V High output voltage on Port 0 pins OH1 V High output voltage on Port 0 pins OH2 V High output voltage on Port 1 pins OH3 V High output voltage on ...
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DC Flash Write Specifications This table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4. 5.25 V and –40 °C < TA < 85 °C, 3. 3.6 V and –40 °C < ...
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AC Electrical Specifications AC Chip-Level Specifications Table 10. 5-V and 3.3-V AC Chip-Level Specifications Parameter Description F Internal low-speed oscillator (ILO) 32K1 frequency t External reset pulse width XRST t Time from end of POR to CPU executing POWERUP code ...
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Specifications Parameter Description SCL clock frequency SCL Hold time (repeated) START condition. HDSTA After this period, the first clock pulse is generated LOW period ...
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Appendix – Examples of Frequently Used I Sl Requirement No. 1 Enter into setup mode 2 Enter into normal mode 3 Load factory defaults to RAM registers software reset 5 Save current configuration to flash 6 Load ...
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Ordering Information Table 14.Key Features and Ordering Information Package Ordering Code Diagram CY8C20110-LDX2I 001-09116 16 QFN CY8C20110-SX2I 51-85068 16 SOIC CY8C20180-LDX2I 001-09116 16 QFN CY8C20180-SX2I 51-85068 CY8C20160-LDX2I 001-09116 16 QFN CY8C20160-SX2I 51-85068 CY8C20140-LDX2I 001-09116 16 QFN CY8C20140-SX2I 51-85068 CY8C20142-SX1I 51-85066 ...
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Package Diagrams Document Number: 001-54606 Rev. *E Figure 13. 16-pin QFN 3 × (Sawn) Figure 14. 16-pin (150--mil) SOIC CY8C20110, CY8C20180 CY8C20160, CY8C20140 CY8C20142 001-09116 *E 51-85068 *C Page [+] Feedback ...
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Document Number: 001-54606 Rev. *E Figure 15. 8-pin (150--mil) SOIC CY8C20110, CY8C20180 CY8C20160, CY8C20140 CY8C20142 51-85066 *D Page [+] Feedback ...
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Acronyms Acronyms Used Table 17 lists the acronyms that are used in this document. Table 17. Acronyms Used in this Datasheet Acronym Description AC alternating current CMOS complementary metal oxide semiconductor DC direct current EEPROM electrically erasable programmable read-only memory ...
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Glossary active high 1. A logic signal having its asserted state as the logic 1 state logic signal having the logic 1 state as the higher voltage of the two states. analog blocks The basic programmable opamp circuits. ...
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Glossary (continued) compiler A program that translates a high level language, such as C, into machine language. configuration In PSoC devices, the register space accessed when the XIO bit, in the CPU_F register, is set to space ‘1’. crystal oscillator ...
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Glossary (continued) ICE The in-circuit emulator that allows you to test the project in a hardware environment, while viewing the debugging device activity in a software environment (PSoC Designer). input/output (I/O) A device that introduces data into or extracts data ...
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Glossary (continued) port A group of pins, usually eight. Power on reset A circuit that forces the PSoC device to reset when the voltage is lower than a pre-set level. This is a type of (POR) hardware reset. ® PSoC ...
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Glossary (continued) tri-state A function whose output can adopt three states and Z (high-impedance). The function does not drive any value in the Z state and, in many respects, may be considered to be disconnected from the rest ...
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Document History Page Document Title: CY8C20110, CY8C20180, CY8C20160, CY8C20140, CY8C20142 CapSense Button Capacitive Controllers Document Number: 001-54606 Orig. of Revision ECN Change ** 2741726 SLAN/FSU *A 2821828 SSHH/FSU *B 2892629 NJF *C 3002214 SLAN *D 3042142 ARVM *E 3085081 NJF ...
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... Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement ...