EA-OEM-315 Embedded Artists, EA-OEM-315 Datasheet

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... To optimize system power consumption, the LPC3141/3143 have multiple power domains and a very flexible Clock Generation Unit (CGU) that provides dynamic clock gating and scaling. 2. Features and benefits 2.1 Key features CPU platform 270 MHz, 32-bit ARM926EJ-S ...

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... Host/OTG All information provided in this document is subject to legal disclaimers. Rev. 0.16 — 27 May 2010 LPC3141/3143 Version MCI Temperature SDHC/ range SDIO/ CE-ATA −40 °C to +85 °C 2 each yes −40 °C to +85 °C 2 each yes © NXP B.V. 2010. All rights reserved ...

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NXP Semiconductors 4. Block diagram JTAG interface LPC3141/3143 TEST/DEBUG INTERFACE ARM926EJ-S master slave INTERRUPT CONTROLLLER slave MPMC slave slave MCI SD/SDIO AHB TO APB BRIDGE 0/ ASYNC APB slave group 0 WDT SYSTEM CONTROL CGU IOCONFIG 10-bit ADC EVENT ROUTER ...

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... ADC10B_GPA2 14 ADC10B_GPA0 Row C 1 EBI_D_7 2 EBI_D_11 5 mGPIO9 6 VDDI 9 VPP 10 I2C_SDA0 13 VDDE_IOC 14 ADC10B_GPA3 Row D 1 EBI_D_5 2 EBI_D_6 5 VDDE_IOC 6 VSSE_IOC 9 VSSE_IOC 10 I2C_SCL0 13 BUF_TCK 14 BUF_TMS LPC3141_3143 Preliminary data sheet ball A1 LPC3141/3143 index area 002aae082 Transparent top view Pin Symbol 3 EBI_D_9 7 SPI_CS_OUT0 11 VSSI - - 3 EBI_A_0_ALE 7 SPI_MOSI ...

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NXP Semiconductors Table 3. Pin allocation table …continued Pin Symbol Pin Symbol Row E 1 EBI_D_3 2 EBI_D_4 5 VDDE_IOA 6 mNAND_RYBN0 9 VSSA12 10 VDDA12 13 I2C_SCL1 14 I2STX_BCK1 Row F 1 EBI_D_2 2 EBI_D_1 5 VDDE_IOA 10 SCAN_TDO ...

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NXP Semiconductors Table 3. Pin allocation table …continued Pin Symbol Pin Symbol Row P 1 USB_VDDA33 2 USB_DP 5 mLCD_DB_7 6 mLCD_DB_3 9 mLCD_DB_1 10 TMS 13 TRST_N 14 mUART_RTS_N Table 4. Pin description Pin names with prefix m are ...

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... USB PLL supply. Supply - PS3 USB analog supply for driver. Supply - PS3 USB analog supply for PHY. Ground - CG1 USB analog ground for clean reference for on chip termination resistors. Ground - CG1 USB analog ground. Ground - CG1 USB analog ground for clean reference. DI I:PD DIO1 JTAG selection ...

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NXP Semiconductors Table 4. Pin description …continued Pin names with prefix m are multiplexed pins. See Pin name BGA Digital Ball I/O level [1] Serial Peripheral Interface (SPI) [4] SPI_CS_OUT0 A7 SUP3 [4] SPI_SCK A8 SUP3 [4] SPI_MISO C8 SUP3 ...

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... DO O DIO4 LCD 6800 enable or 8080 read enable (active HIGH DIO4 LCD instruction register (LOW)/data register (HIGH) select DIO4 LCD 6800 read/write select or 8080 write enable (active HIGH). DIO O DIO4 LCD data 0. DIO O DIO4 LCD data 1. DIO O DIO4 LCD data 2. ...

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NXP Semiconductors Table 4. Pin description …continued Pin names with prefix m are multiplexed pins. See Pin name BGA Digital Ball I/O level [ S/digital audio output [4] mI2STX_DATA0 M13 SUP3 [4] mI2STX_BCK0 M12 SUP3 [4] mI2STX_WS0 M11 ...

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... SPI_CS_OUT2). [6] The polyfuses get unintentionally burned at random if VPP is powered to 2 greater before the VDDI is powered up to minimum nominal voltage. This will destroy the sample because randomly blowing security fuses will lock the sample and also can corrupt the AES key. For this reason it is recommended that VPP be powered by SUP1 at power on. ...

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... Section 6.28.3.) Description Bidirectional 3.3 V; 3-state output slew rate control; plain input; CMOS with hysteresis; programmable pull-up, pull-down, repeater Bidirectional 5 V; plain input; 3-state output; CMOS with programmable hysteresis; programmable pull-up, pull-down, repeater Bidirectional 1 3.3 V; plain input; 3-state output; programmable hysteresis; programmable pull-up, pull-down, repeater ...

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... The ARM926EJ-S is intended for multi-tasking applications where full memory management, high performance, and low power are important. This module has the following features: • ARM926EJ-S processor core which uses a five-stage pipeline consisting of fetch, decode, execute, memory and write stages. The processor supports both the 32-bit ARM and 16-bit Thumb instruction sets, which allows a trade off between high performance and high code density ...

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... LPC3143 only. Fig 3. LPC3141/3143 memory map 6.3 JTAG The Joint Test Action Group (JTAG) interface allows the incorporation of the LPC3141/3143 in a JTAG scan chain. This module has the following features: LPC3141_3143 Preliminary data sheet 0xFFFF FFFF 0x8000 0000 0x7000 0800 APB4 domain ...

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... AES block to support secure (encrypted) code execution (see Before data is written from the buffer to the NAND flash, optionally it is first protected by an error correction code generated by the ECC module. After data is read from the NAND flash, the error correction module corrects errors, and/or the AES decryption module can decrypt data ...

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... MPMC. This enables the MPMC registers to be situated in memory with other system peripheral registers. • Low transaction latency. • Read and write buffers to reduce latency and to improve performance, particularly for un-cached processors. • Static memory features include: – asynchronous page mode read – ...

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... The internal static ROM is used to store the boot code of the LPC3141/3143. After a reset, the ARM processor will start its code execution from this memory. The LPC3143 ROM memory has the following features: • Supports secure booting from SPI flash, NAND flash, SD/SDHC/MMC cards, UART, and USB (DFU class) interfaces. • ...

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... UART Test [1] For security reasons this mode is disabled when JTAG security feature is used. 6.8 Internal RAM memory The ISRAM (Internal Static RAM Memory) controller module is used as controller between the AHB bus and the internal RAM memory. The internal RAM memory can be used as ...

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... Suspend and resume operations. • SDIO read-wait. • Individual clock and power ON/OFF features to each card. • Maximum clock speed of 52 MHz (MMC 4.1). • Supports CE-ATA 1.1. • Supports 1-bit, 4-bit, and 8-bit MMC cards and CE-ATA devices. ...

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... The DMA controller has 12 channels. • Scatter-gather is used to gather data located at different areas of memory. Two channels are needed per scatter-gather action. • Supports byte, half-word, and word transfers and correctly aligns them over the AHB bus. ...

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... The ARM core supports two distinct levels of priority on all interrupt sources, FIQ for high priority interrupts and IRQ for normal priority interrupts. • Software interrupt request capability associated with each request input. • Visibility of interrupts request state before masking. • ...

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NXP Semiconductors Multiple masters can have access to different slaves at the same time. Figure 5 gives an overview of the multi-layer AHB configuration in the LPC3141/3143. AHB masters and slaves are numbered according to their AHB port number. LPC3141_3143 ...

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NXP Semiconductors ARM DMA 926EJ-S master MULTI-LAYER AHB MATRIX = master/slave connection supported by matrix (1) AES is available for LPC3143 only. Fig 5. LPC3141/3143 multi-layer AHB matrix connections LPC3141_3143 Preliminary data sheet USB-OTG AHB MASTER 3 ...

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... NXP Semiconductors This module has the following features: • Supports all combinations of 32-bit masters and slaves (fully connected interconnect matrix). • Round-Robin priority mechanism for bus arbitration: all masters have the same priority and get bus access in their natural order. • ...

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... The clock generation unit generates all clock signals in the system and controls the reset signals for all modules. The structure of the CGU is shown in generated by the CGU belongs to one of the domains. Each clock domain is fed by a single base clock that originates from one of the available clock sources. Within a clock domain, fractional dividers are available to divide the base clock to a lower frequency ...

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... NXP Semiconductors – Each base clock can be programmed to have any one of the clock sources as an input clock. – Fractional dividers can be used to divide a base clock by a fractional number to a lower clock frequency. – Fractional dividers support clock stretching to obtain a (near) 50% duty cycle output clock. • ...

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... Analog-to-Digital Converter (ADC10B) This module is a 10-bit successive approximation ADC with an input multiplexer to allow for multiple analog signals on its input. A common use of this module is to read out multiple keys on one input from a resistor network. This module has the following features: • ...

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... Direct events will disappear when the input becomes inactive. • Latched events will remain active until they are explicitly cleared. • Each input can be masked globally for all inputs at once. • Each input can be masked for each output individually. • Event detect status can be read for each output separately. ...

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... The Secure One-Time Programmable Memory can be used for storing non-volatile information like serial number, security bits, etc. It consists of a polyfuse array, embedded data registers, and control registers. One of the main features of the OTP is storing a security key and a unique ID. This module has the following features: • ...

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... Texas Instruments SSI (Synchronous Serial Interface) frame format with a word size of 4 bit to 16 bit. • Receive FIFO and transmit FIFO of 64 half-words each. • Serial clock rate master mode maximum 45 MHz. • Serial clock rate slave mode maximum 25 MHz. ...

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... I2C0 interface: The I open-drain pins. This interface supports functions described in the I specification for speeds up to 400 kHz. This includes multi-master operation and allows powering off this device in a working system while leaving the I functional. • I2C1 interface: The I with a single-master I I/Os also do not support multi-master I • ...

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... I2STX_0 output and the PCM interface The pin interface multiplexing is subdivided into five categories: storage, video, audio, NAND flash, and UART related pin multiplexing. Each category supports several modes, which can be selected by programming the corresponding registers in the SysCReg. 6.28.1 Pin connections Table 10 ...

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NXP Semiconductors Table 10. Pin descriptions of multiplexed pins Pin Name Default Signal Alternate Signal Description mLCD_DB_3 LCD_DB_3 EBI_A_3 mLCD_DB_4 LCD_DB_4 EBI_A_4 mLCD_DB_5 LCD_DB_5 EBI_A_5 mLCD_DB_6 LCD_DB_6 EBI_A_6 mLCD_DB_7 LCD_DB_7 EBI_A_7 mLCD_DB_8 LCD_DB_8 EBI_A_8 mLCD_DB_9 LCD_DB_9 EBI_A_9 mLCD_DB_10 LCD_DB_10 EBI_A_10 ...

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... MCI_DAT_5 — MCI card data input/output line 5. NAND_RYBN2 — NAND flash controller Read/Not busy signal 2 MCI_DAT_6 — MCI card data input/output line 6. NAND_RYBN3 — NAND flash controller Read/Not busy signal 3. MCI_DAT_7 — MCI card data input/output line 7. I2STX_DATA0 — I2S interface 0 transmit data signal. ...

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NXP Semiconductors control NAND_NCS_[0:3] control NAND_RYBN[0:3] NAND FLASH INTERFACE control EBI_NCAS_BLOUT_0 3 EBI_NRAS_BLOUT_1 EBI_DQM_0_NOE MPMC LCD Fig 9. Diagram of LCD and MPMC multiplexing Figure 9 only shows the signals that are involved in pad-muxing, so not all interface signals ...

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... Free-running timer: The timer generates an interrupt when the counter reaches zero. The timer wraps around to 0xFFFF FFFF and continues counting down. – Periodic timer: The timer generates an interrupt when the counter reaches zero. It reloads the value from a load register and continues counting down from that value ...

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... Supports single 24 bit transfers to/from the left or right FIFO. • Supports 32-bit interleaved transfers, with the lower 16 bits representing the left audio sample, and the higher 16 bits representing the right audio sample. • Supports two 16-bit audio samples combined in a 32-bit word (2 left or 2 right samples) to reduce busload. • ...

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... The following applies to the limiting values: a) This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static charge. Nonetheless suggested that conventional precautions be taken to avoid applying greater than the rated maximum. b) Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to V otherwise noted ...

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... I pull-down current pd LPC3141_3143 Preliminary data sheet Conditions Min on pin 2.7 ADC10B_VDDA33; for 10-bit ADC (SUP 3) on pin VPP; write 3.0 on pin VPP; read 1.1 on pin USB_VBUS - (SUP5) on pin USB_VDDA33 3.0 (SUP 3) on pin 2.7 USB_VDDA33_DRV (SUP 3); driver on pin 1.1 USB_VDDA12_PLL ...

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NXP Semiconductors Table 12: Static characteristics − ° ° +85 C unless otherwise specified. amb Symbol Parameter C input capacitance i Output pins and I/O pins configured as output V output voltage O V HIGH-level ...

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... Symbol Parameter V HIGH-level input IH voltage V LOW-level input IL voltage V hysteresis voltage hys V LOW-level output OL voltage I input leakage current LI USB V common-mode input i(cm) voltage V differential input i(dif) voltage [1] The parameter values specified are simulated values. LPC3141_3143 Preliminary data sheet Conditions Min [1] 0.7VDDE_IOC ...

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... See D [5] The integral non-linearity ( the peak difference between the center of the steps of the actual and the ideal transfer curve after L(adj) appropriate adjustment of gain and offset errors. See [6] ...

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... E O (1) Example of an actual transfer curve. (2) The ideal transfer curve. (3) Differential linearity error ( (4) Integral non-linearity (E ). L(adj) (5) Center of a step of the actual transfer curve. Fig 10. ADC characteristics LPC3141_3143 Preliminary data sheet (2) (1) (5) (4) (3) 1 LSB (ideal) 1018 1019 ...

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NXP Semiconductors Fig 11. Suggested 10-bit ADC interface LPC3141_3143 Preliminary data sheet LPC31XX tbd kΩ ADC SAMPLE tbd pF tbd pF V SSA All information provided in this document is subject to legal disclaimers. Rev. 0.16 — 27 May 2010 ...

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... ADC10B_VDDA33 = 3.3 V USB_VDDA33 = 3.3 V USB_VDDA_DRV = 3 Power dissipation Total for supply domains SUP1, SUP3, SUP4, SUP8 External SDRAM based system (operating frequency 270 MHz (core)/ 90 MHz (bus)); heavy SDRAM load power; [2][3] with dynamic clock scaling I Supply current core; VDDI = 1 all other SUP1 supplies: VDDA12 = 1.2 V; ...

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NXP Semiconductors Table 14. Power consumption …continued Symbol Parameter Conditions External SDRAM based system (operating frequency 270 MHz (core)/ 90 MHz (bus)); normal mode power; without [4] dynamic clock scaling I Supply current core; VDDI = 1 all ...

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... Mhz oscillator running; PLLs off; SYS_BASE and AHB_APB0_BASE Base domain clocks are enabled, driven by 12 Mhz oscillator; all peripherals off; SUP4 buffers set to input w/PD; SUP8 and SUP3 buffers set to input w/repeater. Shutting off the 12 Mhz osc will reduce power to 1.4 mW (requires a RSTIN_N to run again). ...

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... Symbol Parameter t address set-up time su(A) t address hold time h(A) t access cycle time cy(a) t write enable pulse width w(en)W t read enable pulse width w(en)R rise time fall time f t data input set-up time su(D) t data input hold time h(D) t data output valid delay time ...

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... Typ Max Unit 1 × LCDCLK - - ns 2 × LCDCLK - - ns 5 × LCDCLK [ <tbd> <tbd> −1 × LCDCLK - - ns 2 × LCDCLK - - ns 2 × LCDCLK - - ns 2 × LCDCLK - - ns t h(A) t h(D) read access t dis(Q) write access 002aae208 © NXP B.V. 2010. All rights reserved ...

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... Timing is determined by the LCD Interface Control Register fields SERIAL_CLK_SHIFT = 3; SERIAL_READ_POS = 3. See the LPC314x user manual. mLCD_CSB mLCD_RS mLCD_DB13 (serial clock) mLCD_DB14 (serial data in) mLCD_DB15 (serial data out) Fig 14. LCD timing (serial mode) ...

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... Dynamic characteristics: static external memory interface − ° ° pF +85 C, unless otherwise specified amb Symbol Parameter Common to read and write cycles t CS LOW to address valid CSLAV time Read cycle parameters t OE LOW to address valid OELAV time t BLS LOW to address valid BLSLAV time ...

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... NXP Semiconductors EBI_NSTCS_X t CSLAV EBI_A_[15:0] EBI_DQM_0_NOE t t EBI_NCAS_BLOUT_0 EBI_NRAS_BLOUT_1 t EBI_D_[15:0] Fig 15. External memory read access to static memory LPC3141_3143 Preliminary data sheet t OELAV t OELOEH CSLOEL BLSLAV t BLSLBLSH CSLBLSL All information provided in this document is subject to legal disclaimers. Rev. 0.16 — 27 May 2010 LPC3141/3143 ...

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NXP Semiconductors EBI_NSTCS_X EBI_A_[15:0] EBI_D_[15:0] EBI_NWE EBI_NCAS_BLOUT_0 EBI_NRAS_BLOUT_1 Fig 16. External memory write access to static memory LPC3141_3143 Preliminary data sheet t CSLAV t CSLDV t WELWEH t CSLWEL t WELDV t BLSLBLSH t CSLBLSL All information provided in this ...

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... Parameters are valid over operating temperature range unless otherwise specified. All values valid for pads set to high slew rate. VDDE_IOA = VDDE_IOB = 1.8 ± 0.15 V. VDDI = 1.2 ± 0.1 V. [2] [3] Refer to the LPC3141/3143 user manual for the programming of MPMCDynamicReadConfig and SYSCREG_MPMP_DELAYMODES registers [4] f ...

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... NXP Semiconductors T CLCL t CHCX EBI_CLKOUT EBI_NRAS_BLOUT EBI_NCAS_BLOUT EBI_NWE EBI_CKE EBI_NDYCS EBI_DQMx EBI_A_[15:2] EBI_D_[15:0] EBI_CKE is HIGH. Fig 17. SDRAM burst read timing LPC3141_3143 Preliminary data sheet t CLCX t t d(o) h(o) READ NOP NOP NOP t d(o) t h(A) BANK su(D) h(D) COLUMN DATA n CAS DATA n+1 LATENCY = 2 All information provided in this document is subject to legal disclaimers ...

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T CLCL t CLCX t CHCX EBI_CLKOUT EBI_CKE EBI_NRAS_BLOUT EBI_NCAS_BLOUT EBI_NWE EBI_CKE EBI_NDYCS EBI_DQMx EBI_A_[15:2] EBI_D_[15:0] Fig 18. SDRAM bank activate and write timing t ...

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... NANDFLASH_NAND_CLK, see LPC314x user manual. HCLK [2] See registers NandTiming1 and NandTiming2 in the LPC314x user manual. [3] Each timing parameter can be set from 7 nand_clk clock cycles to 1 nand_clk clock cycle. (A programmed zero value is treated as a one). Fig 19. NAND flash controller write and read timing LPC3141_3143 Preliminary data sheet ° ...

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NXP Semiconductors 9.5 Crystal oscillator Table 21: Dynamic characteristics: crystal oscillator Symbol Parameter f oscillator frequency osc δ clock duty cycle clk C oscillator capacitance xtal t start-up time startup P drive power drive 9.6 SPI Table 22. Dynamic characteristics ...

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NXP Semiconductors SCK (CPOL = 0) SCK (CPOL = 1) Fig 20. SPI master timing (CPHA = 1) Fig 21. SPI master timing (CPHA = 0) LPC3141_3143 Preliminary data sheet t SPICLK t SPISEDV DATA VALID MOSI MISO DATA VALID ...

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... SCK (CPOL = 1) t MOSI DATA VALID t SPISEDV MISO DATA VALID [1] Conditions Min = 25 ° amb measured in SPI Master mode; see Figure 24 All information provided in this document is subject to legal disclaimers. Rev. 0.16 — 27 May 2010 LPC3141/3143 t t SPICLKH SPICLKL t t SPIDSU SPIDH DATA VALID ...

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NXP Semiconductors shifting edges SCK MOSI MISO Fig 24. MISO line set-up time in SSI Master mode LPC3141_3143 Preliminary data sheet t su(SPI_MISO) All information provided in this document is subject to legal disclaimers. Rev. 0.16 — 27 May 2010 ...

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NXP Semiconductors 2 9.7 I S-interface Table 24. Dynamic characteristics: I − ° ° +85 C for industrial applications amb Symbol Parameter common to input and output T clock cycle time cy(clk) t rise time ...

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... HIGH period of the SCL clock HIGH t data set-up time SU;DAT t set-up time for a repeated START SU;STA condition t set-up time for STOP condition SU;STO [1] Parameters are valid over operating temperature range unless otherwise specified. Typical ratings are not guaranteed. The values listed are at room temperature (25 °C), nominal supply voltages. ...

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NXP Semiconductors SDA t t BUF LOW SCL HD;STA Remark: Signals SDA and SCL correspond to pins I2C_SDAx and I2C_SCLx ( 1). 2 Fig 27. I C-bus pins clock timing LPC3141_3143 Preliminary data sheet t ...

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NXP Semiconductors 9.9 USB interface Table 26. Dynamic characteristics: USB pins (high-speed) Ω pF 1 DD(IO) Symbol Parameter t rise time r t fall time f t differential ...

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Application information Table 28. LCD panel connections TFBGA pin # Pin name K8 mLCD_CSB/EBI_NSTCS_0 L8 mLCD_E_RD/EBI_CKE P8 mLCD_RS/EBI_NDYCS N9 mLCD_RW_WR/EBI_DQM_1 N8 mLCD_DB_0/EBI_CLKOUT P9 mLCD_DB_1/EBI_NSTCS_1 ...

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NXP Semiconductors 11. Marking Table 29. LPC3141/3143 Marking Line A LPC3141_3143 Preliminary data sheet Marking Description LPC3141/3143 BASIC_TYPE All information provided in this document is subject to legal disclaimers. Rev. 0.16 — 27 May 2010 LPC3141/3143 © NXP B.V. 2010. ...

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... NXP Semiconductors 12. Package outline TFBGA180: thin fine-pitch ball grid array package; 180 balls ball A1 index area ball index area DIMENSIONS (mm are the original dimensions) UNIT 1.20 0.40 0.50 max 0.80 mm nom 1.06 0.35 0.71 0.45 min 0.95 0.30 0.65 0.40 OUTLINE ...

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... Field Programmable Gate Array Galois Field Input Output Configuration ISDN Oriented Modular Infrared Data Association Internal Static RAM Internal Static ROM Joint Test Action Group Least Significant Bit Memory Card Interface Microcontroller Unit Multi-Media Card Multi-Port Memory Controller On-The-Go Pulse Code Modulation Physical Layer ...

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... USB UTMI WDT LPC3141_3143 Preliminary data sheet …continued Description Random Number Generator Read-Only Memory Secure Digital Secure Digital High Capacity Secure Digital Input Output Single Data Rate Synchronous Dynamic Random Access Memory Single Ended 0 Serial IrDA Serial Peripheral Interface Serial Synchronous Interface ...

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... NXP Semiconductors 14. Revision history Table 31: Revision history Document ID Release date LPC3141_3143 v.0.16 <tbd> • Modifications: Reset state of JTAG pins and GPIO0, GPIO1, and GPIO2 pins updated in • Document template updated. • Digital I/O level for pin CLOCK_OUT corrected in • Power consumption data updated in LPC3141_3143_0.15 < ...

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... NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’ ...

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... Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: LPC3141_3143 Preliminary data sheet whenever customer uses the product for automotive applications beyond NXP Semiconductors’ specifications such use shall be solely at customer’s ...

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... NXP Semiconductors 17. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 2.1 Key features . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 3.1 Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 2 4 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 5 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 6 Functional description . . . . . . . . . . . . . . . . . . 13 6.1 ARM926EJ 6.2 Memory map 6.3 JTAG 6.4 NAND flash controller . . . . . . . . . . . . . . . . . . . 15 6.5 Multi-Port Memory Controller (MPMC) ...