EA-OEM-410 Embedded Artists, EA-OEM-410 Datasheet
EA-OEM-410
Specifications of EA-OEM-410
Related parts for EA-OEM-410
EA-OEM-410 Summary of contents
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... PWMs, a motor control PWM, six general purpose timers with capture inputs and compare outputs, a Secure Digital (SD) interface, and a 10-bit Analog-to-Digital Converter (ADC) with a touch screen sense option. 2. Features and benefits ARM926EJS processor, running at CPU clock speeds up to 266 MHz. Vector Floating Point (VFP) coprocessor. ...
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... NXP Semiconductors Multi-layer AHB system that provides a separate bus for each AHB master, including both an instruction and data bus for the CPU, two data busses for the DMA controller, and another bus for the USB controller, one for the LCD, and a final one for the Ethernet MAC ...
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... Another PLL allows operation from the 32 kHz RTC clock rather than the external crystal. Boundary scan for simplified board testing. User-accessible unique serial ID number for each chip. 296 pin TFBGA package with a 15 × 15 × 0.7 mm body. 3. Applications ...
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NXP Semiconductors 4. Ordering information Table 1. Ordering information [1] Type number Package Name [2] LPC3220FET296 TFBGA296 [2] LPC3230FET296 TFBGA296 [2] LPC3240FET296 TFBGA296 [2] LPC3250FET296 TFBGA296 [3] LPC3220FET296/01 TFBGA296 [3] LPC3230FET296/01 TFBGA296 [3] LPC3240FET296/01 TFBGA296 [3] LPC3250FET296/01 TFBGA296 F = ...
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NXP Semiconductors 5. Block diagram ETB ETM 9 VFP9 ARM D-CACHE I-CACHE 9EJS D-SIDE I-SIDE MMU CONTROLLER CONTROLLER DATA INSTRUCTION master layer 0 1 slave port 32-bit AHB matrix ...
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... I2S1TX_CLK/MAT3[0] A7 MS_DIO1/MAT0[1] A10 SPI2_DATIN/MISO1/ [1] LCDVD[21] /GPI_27 [1] A13 GPO_21/U4_TX/LCDVD[3] [1] A16 GPO_6/LCDVD[18] Row B B4 I2S1TX_WS/CAP3[0] B7 MS_SCLK/MAT2[0] [1] B10 SPI2_CLK/SCK1/LCDVD[23] [1] B13 GPO_13/MCOB1/LCDDCLK B16 GPI_8/KEY_COL6/ [2] SPI2_BUSY/ENET_RX_DV Row C C1 FLASH_RD C4 USB_ATX_INT C7 GPI_6/HSTIM_CAP/ [2] ENET_RXD2 LPC3220_30_40_50_1 Product data sheet ball A1 index area Transparent top view Pin Symbol Pin A3 A5 ...
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NXP Semiconductors Table 3. Pin allocation table (TFBGA296) Pin Symbol C10 SPI1_DATIN/MISO0/GPI_25/ MCI1 [1] C13 GPO_8/LCDVD[8] C16 GPI_0/I2S1RX_SDA Row D D1 FLASH_RDY D4 GPO_1 D7 P0[1]/I2S1RX_WS [1] D10 GPO_16/MCOB0/LCDENAB / [1] LCDM D13 GPI_7/CAP4[0]/MCABORT [2] D16 KEY_ROW3/ENET_TX_EN Row E E1 ...
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NXP Semiconductors Table 3. Pin allocation table (TFBGA296) Pin Symbol [1] H16 HIGHCORE/LCDVD[17] Row J J1 EMC_A[20]/P1[20] J4 EMC_A[23]/P1[23] J7 VDD_CORE J13 VDD_IOA J16 JTAG_TDI Row K K1 EMC_A[19]/P1[19] K4 EMC_A[17]/P1[17] K7 VDD_EMC K13 VSS_IOA K16 U1_TX Row L L1 ...
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NXP Semiconductors Table 3. Pin allocation table (TFBGA296) Pin Symbol P7 VSS_EMC P10 VSS_EMC P13 VSS_AD P16 RTCX_IN Row R R1 EMC_A[13]/P1[13] R4 EMC_WR R7 EMC_D[1] R10 EMC_D[24]/P2[5] R13 TS_XP R16 VSS_PLLUSB Row T T1 EMC_DQM[2] T4 EMC_CLKIN T7 EMC_D[11] ...
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NXP Semiconductors 6.2 Pin description Table 4. Pin description Symbol Pin Power supply domain ADIN0/TS_YM U15 VDD_AD ADIN1/TS_XM T14 VDD_AD ADIN2/TS_AUX_IN V16 VDD_AD DBGEN G14 VDD_IOD EMC_A[0]/P1[0] L3 VDD_EMC EMC_A[1]/P1[1] L4 VDD_EMC EMC_A[2]/P1[2] M1 VDD_EMC EMC_A[3]/P1[3] M2 VDD_EMC EMC_A[4]/P1[4] M3 ...
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NXP Semiconductors Table 4. Pin description …continued Symbol Pin Power supply domain EMC_A[15]/P1[15] L1 VDD_EMC EMC_A[16]/P1[16] K3 VDD_EMC EMC_A[17]/P1[17] K4 VDD_EMC EMC_A[18]/P1[18] K2 VDD_EMC EMC_A[19]/P1[19] K1 VDD_EMC EMC_A[20]/P1[20] J1 VDD_EMC EMC_A[21]/P1[21] J2 VDD_EMC EMC_A[22]/P1[22] J3 VDD_EMC EMC_A[23]/P1[23] J4 VDD_EMC EMC_BLS[0] ...
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NXP Semiconductors Table 4. Pin description …continued Symbol Pin Power supply domain EMC_D[9] U6 VDD_EMC EMC_D[10] V6 VDD_EMC EMC_D[11] T7 VDD_EMC EMC_D[12] U7 VDD_EMC EMC_D[13] V7 VDD_EMC EMC_D[14] T8 VDD_EMC EMC_D[15] U8 VDD_EMC EMC_D[16]/ V8 VDD_EMC EMC_DQS0 EMC_D[17]/ R9 VDD_EMC ...
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... Flash data bus, bit 3 I/O: BK Flash data bus, bit 4 I/O: BK Flash data bus, bit 5 I/O: BK Flash data bus, bit 6 I/O: BK Flash data bus, bit 7 O Flash read enable I Flash ready (from flash device) O Flash write enable I General purpose input Receive data I General purpose input 1 I ...
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NXP Semiconductors Table 4. Pin description …continued Symbol Pin Power supply domain GPI_7/CAP4[0]/ D13 VDD_IOD MCABORT GPI_8/KEY_COL6/ B16 VDD_IOD SPI2_BUSY/ ENET_RX_DV GPI_9/KEY_COL7/ E12 VDD_IOD ENET_COL GPI_19/U4_RX B15 VDD_IOD GPI_28/U3_RI N17 VDD_IOA GPIO_0 A12 VDD_IOD GPIO_1 A11 VDD_IOD GPIO_2/ D9 VDD_IOD ...
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NXP Semiconductors Table 4. Pin description …continued Symbol Pin Power supply domain GPO_5 B3 VDD_IOC GPO_6/ A16 VDD_IOD LCDVD[18] GPO_7/ A15 VDD_IOD LCDVD[2] GPO_8/ C13 VDD_IOD LCDVD[8] GPO_9/ C12 VDD_IOD LCDVD[9] GPO_10/ E11 VDD_IOD MCOB2/ LCDPWR GPO_11 E8 VDD_IOB GPO_12/ ...
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NXP Semiconductors Table 4. Pin description …continued Symbol Pin Power supply domain GPO_22/ E10 VDD_IOD U7_HRTS/ LCDVD[14] GPO_23/ M16 VDD_IOA U2_HRTS/ U3_RTS HIGHCORE/ H16 VDD_IOD LCDVD[17] I2C1_SCL A5 VDD_IOB I2C1_SDA B6 VDD_IOB I2C2_SCL A3 VDD_IOC I2C2_SDA E4 VDD_IOC I2S1TX_CLK/ A4 ...
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NXP Semiconductors Table 4. Pin description …continued Symbol Pin Power supply domain KEY_COL5/ F16 VDD_IOD ENET_RXD1 KEY_ROW0/ E15 VDD_IOD ENET_TX_ER KEY_ROW1/ E14 VDD_IOD ENET_TXD2 KEY_ROW2/ F14 VDD_IOD ENET_TXD3 KEY_ROW3/ D16 VDD_IOD ENET_TX_EN KEY_ROW4/ C17 VDD_IOD ENET_TXD0 KEY_ROW5/ C18 VDD_IOD ENET_TXD1 ...
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NXP Semiconductors Table 4. Pin description …continued Symbol Pin Power supply domain P0[2]/ M17 VDD_IOA I2S0RX_SDA/ LCDVD[4] P0[3]/ M18 VDD_IOA I2S0RX_CLK/ LCDVD[5] P0[4]/ L15 VDD_IOA I2S0RX_WS/ LCDVD[6] P0[5]/ L16 VDD_IOA I2S0TX_SDA/ LCDVD[7] P0[6]/ L17 VDD_IOA I2S0TX_CLK/ LCDVD[12] P0[7]/ L18 VDD_IOA ...
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... Test clock 2 out I/O HS UART 1 receive I/O Timer 1 capture input 0 I/O General purpose input bit UART 1 transmit I/O HS UART 2 Clear to Send input I UART 3 Clear to Send I/O General purpose input bit 16 I/O HS UART 2 receive I/O UART 3 data set ready I/O General purpose input bit 17 ...
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NXP Semiconductors Table 4. Pin description …continued Symbol Pin Power supply domain U7_RX/ E17 VDD_IOD CAP0[0]/ LCDVD[10]/ GPI_23 U7_TX/ E18 VDD_IOD MAT1[1]/ LCDVD[11] USB_ATX_INT C4 VDD_IOC USB_DAT_VP/ D5 VDD_IOC U5_RX USB_I2C_SCL E5 VDD_IOC USB_I2C_SDA E6 VDD_IOC USB_OE_TP D6 VDD_IOC USB_SE0_VM/ ...
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NXP Semiconductors Table 4. Pin description …continued Symbol Pin Power supply domain VDD_PLL397 T16 VDD_PLL397 VDD_PLLHCLK R17 VDD_PLLHCLK VDD_PLLUSB P15 VDD_PLLUSB VDD_FUSE N14 VDD_FUSE VDD_RTC K14 VDD_RTC VDD_RTCCORE L13 VDD_RTCCORE VDD_RTCOSC N15 VDD_RTCOSC VSS_AD P13 - VSS_CORE G8, - G10, ...
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... O = output. I/O = bidirectional. I bidirectional or high impedance. BK: pin has a bus keeper function that weakly retains the last level driven on an I/O pin when it is switched from output to input. PU: pin has a nominal 50 μA internal pull-up connected. PD: pin has a nominal 50 μA internal pull-down connected. ...
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... Emulation and debugging The LPC3220/30/40/50 supports emulation and debugging via a dedicated JTAG serial port. An Embedded Trace Buffer allows tracing program execution. The dedicated JTAG port allows debugging of all chip features without impact to any pins that may be used in the application. 7.1.3.1 Embedded ICE Standard ARM EmbeddedICE logic provides on-chip debug support ...
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... In this architectural implementation, removing guaranteed central arbitration and allowing more than one bus master to be active at the same time provides better overall microcontroller performance. In the LPC3220/30/40/50, the multi-Layer AHB system has a separate bus for each of seven AHB Masters: • ...
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... NXP Semiconductors 7.2.1 APB Many peripheral functions are accessed by on-chip APBs that are attached to the higher speed AHB. The APB performs reads and writes to peripheral registers in three peripheral clocks. 7.2.2 FAB Some peripherals are placed on a special bus called FAB that allows faster CPU access to those peripheral functions ...
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NXP Semiconductors 4.0 GB off-chip memory 2.0 GB peripherals on AHB matrix slave port 7 1.0 GB peripherals on AHB matrix slave port 6 768 MB peripherals on AHB matrix slave port 5 on-chip memory 0.0 GB Fig 3. LPC3220/30/40/50 ...
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... NAND FLASH. After reset, execution always begins from the internal ROM. The bootstrap software first reads the SERVICE input (GPI_1). If SERVICE is LOW, the bootstrap starts a service boot and can download a program over serial link UART5 to IRAM and transfer execution to the downloaded code. ...
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... The SLC NAND flash controller interfaces to single-level NAND flash devices. DMA page transfers are supported, including a 20-byte DMA read and write FIFO. Hardware support for ECC (Error Checking and Correction) is included for the main data area. Software can correct a single bit error. ...
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... The DMA controls eight DMA channels with hardware prioritization. The DMA controller interfaces to the system via two AHB bus masters, each with a full 32-bit data bus width. DMA operations may be set up for 8-bit, 16-bit, and 32-bit data widths, and can be either big-endian or little-endian ...
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... The USB device controller enables 12 Mbit/s data exchange with a USB host controller. It consists of register interface, serial interface engine, endpoint buffer memory and DMA controller. The serial interface engine decodes the USB data stream and writes data to the appropriate end point buffer memory. The status of a completed USB transfer or error ...
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... Scalable realization of endpoints at run time. • Endpoint maximum packet size selection (up to USB maximum specification) by software at run time. • RAM message buffer size based on endpoint realization and maximum packet size. • Supports bus-powered capability with low suspend current. • Supports DMA transfer on all non-control endpoints. ...
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... Provides programmable timers required for HNP and SRP. • Supports slave mode operation through AHB slave interface. • Supports the OTG ATX from NXP (ISP 1302) or any external CEA-2011OTG specification compliant ATX. 7.6.4 LCD controller The LCD controller provides all of the necessary control signals to interface directly to a variety of color and monochrome LCD panels. Both STN (single and dual panel) and TFT panels can be operated. The display resolution is selectable and can 1024 × ...
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... The interrupt controller is comprised of three basic interrupt controller blocks, supporting a total of 73 interrupt sources. Each interrupt source can be individually enabled/disabled and configured for high or low level triggering, or rising or falling edge triggering. Each interrupt may also be steered to either the FIQ or IRQ input of the ARM9. Raw interrupt status and masked interrupt status registers allow versatile condition evaluation ...
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... USB PLL. The input to the HCLK and USB PLLs may initially be divided down by a pre-divider value ‘N’, which may have the values This pre-divider can allow a greater number of possibilities for the output frequency. Following the PLL input divider is the PLL multiplier. ...
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... The RESET pin is located in the RTC power domain. This means that the RTC power must be present for an external reset to have any effect. The RTC power domain nominally runs from 1 ...
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... Transmitter FIFO trigger points and 16 Bytes. • Register locations conform to the “550” industry standard. • Each standard UART has a fractional rate pre-divider and an internal baud rate generator. • The standard UARTs support three clocking modes: on, off, and auto-clock. The auto-clock mode shuts off the clock to the UART when it is idle. ...
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... C-bus serial I/O controller There are two I can be configured as a master, multi-master or slave supporting up to 400 kHz. The I blocks also support bit addressing. Each has a four word FIFO for both transmit and receive. An interrupt signal is available from each block. LPC3220_30_40_50_1 Product data sheet ⁄ ...
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... Each I 7.8.5.1 Features • The interface has separate input/output channels each of which can operate in master or slave mode. • Capable of handling 8-bit, 16-bit, and 32-bit word sizes. • ...
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... GPIO pins. When the SDRAM bus is configured for 16 data bits the remaining SDRAM data pins may be used as GPIOs. 7.9.1.1 Features • Bit-level set and clear registers allow a single instruction set or clear of any number of bits in one port. • A single register selects direction for pins that support both input and output modes. ...
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... The LPC3220/30/40/50 microcontrollers includes Touch Screen Controller (TSC) hardware, which automatically measures and determines the X and Y coordinates where a touch screen is pressed. In addition, the TSC can measure an analog input signal on the AUX_IN pin. Optionally, the TSC can operate as an Analog-to-Digital Converter (ADC). The ADC supports three channels and uses 10-bit successive approximation to produce results with a resolution of 10 bits in 11 clock cycles ...
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... NXP Semiconductors Two 32-bit match registers are readable and writable by the processor. A match will result in an interrupt provided that the interrupt is enabled. The ONSW output pin can also be triggered by a match event and cause an external power supply to turn on all of the operating voltages way to startup after power has been removed. ...
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... Output frequency kHz when using a 13 MHz peripheral clock. 7.9.8 Motor control pulse width modulator The Motor Control PWM (MCPWM) provides a set of features for three-phase AC and DC motor control applications in a single peripheral. The MCPWM can also be configured for use in other generalized timing, counting, capture, and compare applications. ...
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... The ARM926EJ-S processor also employs an operational state known as Thumb, which makes it ideally suited to high-volume applications with memory restrictions, or applications where code density is an issue. The key idea behind Thumb state is the use of a super-reduced instruction set. Essentially, the ARM926EJ-S processor core has two instruction sets: 1. The standard 32-bit ARM set 2. The 16-bit Thumb set The Thumb set’ ...
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... This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static charge. Nonetheless suggested that conventional precautions be taken to avoid applying greater than the rated maximum. b) Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to V otherwise noted ...
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NXP Semiconductors 10. Static characteristics Table 8. Static characteristics − ° ° +85 C, unless otherwise specified. amb Symbol Parameter Conditions V supply voltage (1.2 V) core supply voltage for DD(1V2) full performance; 266 MHz ...
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NXP Semiconductors Table 8. Static characteristics …continued − ° ° +85 C, unless otherwise specified. amb Symbol Parameter Conditions Power consumption in Run, direct Run, and Stop modes I Run mode supply T DD(run) current ...
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NXP Semiconductors Table 8. Static characteristics …continued − ° ° +85 C, unless otherwise specified. amb Symbol Parameter Conditions I RTC supply current VDD_RTC = DD(RTC) VDD_RTCCORE = VDD_RTCOSC = 1 Input pins ...
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NXP Semiconductors Table 8. Static characteristics …continued − ° ° +85 C, unless otherwise specified. amb Symbol Parameter Conditions I HIGH-level short-circuit V OHS output current V I LOW-level short-circuit V OLS output current V ...
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NXP Semiconductors Table 8. Static characteristics …continued − ° ° +85 C, unless otherwise specified. amb Symbol Parameter Conditions I LOW-level V OL output current OFF-state V OZ output current no ...
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NXP Semiconductors Table 8. Static characteristics …continued − ° ° +85 C, unless otherwise specified. amb Symbol Parameter Conditions V LOW-level 1.2 V outputs output voltage I HIGH-level V OH output current I ...
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... Multi-level NAND controller Single-level NAND controller LCD Ethernet MAC [1] All three Ethernet clocks are in enabled in the MAC_CLK_CTRL register (see LPC32x0 User manual). LPC3220_30_40_50_1 Product data sheet 200 can be switched on or off independent of each other. An internal circuit I DD(run) 0.3 0.3 0.6 0.5 6.3 7.3 1 ...
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NXP Semiconductors 10.4 Power consumption in Run mode Power consumption is shown in conditions from SDRAM. MMU and I-cache/D-cache are enabled. The VFP is turned on but not used. I touchscreen ADC, and UART3 are turned on. All other peripherals ...
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... See D [4] The integral non-linearity ( the peak difference between the center of the steps of the actual and the ideal transfer curve after L(adj) appropriate adjustment of gain and offset errors. See [5] ...
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... E O (1) Example of an actual transfer curve. (2) The ideal transfer curve. (3) Differential linearity error ( (4) Integral non-linearity (E ). L(adj) (5) Center of a step of the actual transfer curve. Fig 6. ADC characteristics LPC3220_30_40_50_1 Product data sheet (2) (1) (5) (4) (3) 1 LSB (ideal) 1018 1019 ...
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... Dynamic characteristics: static external memory interface ° pF 1 amb DD(EMC) Symbol Parameter Common to read and write cycles T clock cycle time CLCL t CS LOW to address valid time CSLAV Read cycle parameters t OE LOW to address valid time OELAV t BLS LOW to address valid time ...
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... Refer to the LPC32x0 user manual EMCStaticWaitRd0-3 register for the programming of WAITRD value. [4] Refer to the LPC32x0 user manual EMCStaticWaitWen0-3 register for the programming of WAITWEN value. [5] Refer to the LPC32x0 user manual EMCStaticWaitWr0-3 register for the programming of WAITWR value. [6] Earliest of CS HIGH, OE HIGH, address change to data invalid. EMC_A[23:0] EMC_CS[3:0] t OELAV EMC_OE ...
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NXP Semiconductors EMC_A[23:0] EMC_CS[3:0] EMC_D[31:0] EMC_WR EMC_BLS[3:0] Fig 8. External memory write access LPC3220_30_40_50_1 Product data sheet t CSLAV t CSLDV t WELDV t WEHDNV t CSLWEL t WELWEH t BLSHDNV t CSLBLSL t BLSLBLSH All information provided in this ...
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NXP Semiconductors 11.3 SDR SDRAM Controller Table 13. EMC SDR SDRAM memory interface dynamic characteristics − ° ° pF +85 C, unless otherwise specified. L amb Symbol Parameter f operating frequency oper ...
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... DQS_DELAY, see LPC32x0 user manual, External Memory Controller Chapter, Section 8 DDR DQS delay calibration for details on configuring this value. [5] Test conditions for measurements: T amb Ω EMC_D[31:0] driving 2 inches of 50 resistors used. EMC pads set to fast slew rate at 1 2.5 V (see SDRAMCLK_CTRL register in the LPC32x0 User manual). ...
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... READ EMC_DQSm (1) delayed EMC_DQSm EMC_D[31:0] (1) The delay of the EMC_DQSm signal is determined by the DQS_DELAY settings. See LPC32x0 user manual, External Memory Controller Chapter, section DDR DQS delay calibration for details on configuring this value. Fig 12. DDR read timing parameters LPC3220_30_40_50_1 Product data sheet ...
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NXP Semiconductors 11.5 USB controller Table 15. Dynamic characteristics USB digital I/O pins − ° ° 3 +85 C, unless otherwise specified. DD(IO) amb Symbol Parameter t bus turnaround time (I/O) TIO ...
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... REHRBL t WE HIGH to R/B LOW time cycle time HIGH hold time pulse width WP [ 1/HCLK HCLK [2] CEA = bitfield TCEA_DELAY[1:0] in register MLC_TIME_REG[25:24 bitfield WR_LOW[3:0] in register MLC_TIME_REG[3: bitfield WR_HIGH[3:0] in register MLC_TIME_REG[7: bitfield RD_LOW[3:0] in register MLC_TIME_REG[11: bitfield RD_HIGH [3:0] in register MLC_TIME_REG[15:12] [ bitfield NAND_TA[2:0] in register MLC_TIME_REG[18:16] ...
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... NXP Semiconductors FLASH_RDY (R/B) Fig 15. MLC NAND flash controller write timing (writing to NAND flash) Fig 16. MLC NAND flash controller read timing (reading from NAND flash) 11.8 SLC NAND flash memory controller Table 18. Dynamic characteristics of SLC NAND flash memory controller − ° ...
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... RE high hold time REH t RE HIGH to output hold time RHOH t RE HIGH to output RHZ high-impedance time t RE pulse width RP t ready to RE LOW time HIGH to R/B LOW time cycle time WC LPC3220_30_40_50_1 Product data sheet …continued Conditions Min [1][2][4][6][8] read ...
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... Rsu = bitfield R_SETUP[3:0] in register SLC_TAC[3:0] for reads [ bitfield R_HOLD[3:0] in register SLC_TAC[7:4] for reads [ bitfield R_WIDTH[3:0] in register SLC_TAC[11:8] for reads [ bitfield R_RDY[3:0] in register SLC_TAC[15:12] for reads [6] Wsu = bitfield W_SETUP[3:0] in register SLC_TAC[19:16] for writes [ bitfield W_HOLD[3:0] in register SLC_TAC[23:20] for writes [ bitfield W_WIDTH[3:0] in register SLC_TAC[27:24] for writes ...
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... ALS ALH FLASH_ALE t t CLS CLH FLASH_CLE FLASH_RDY FLASH_WR FLASH_RD command FLASH_IO[7: FLASH_CE command Fig 18. MLC NAND Flash memory read timing (reading from NAND flash) LPC3220_30_40_50_1 Product data sheet t t ALS ALH t CLS CLR address CEA address All information provided in this document is subject to legal disclaimers. ...
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... Product data sheet command Min 2 × T [1] HCLK - - - - - - - - All information provided in this document is subject to legal disclaimers. Rev. 01.03 — 16 March 2010 LPC3220/30/40/50 16/32-bit ARM microcontrollers t CEA t COH t CLR t WHR t RHOH t RHZ status REA data 002aae446 Typ Max Unit 256 × HCLK © ...
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NXP Semiconductors 11.9.2 Timing diagrams for SPI and SSP (in SPI mode) Fig 20. SPI master timing (CPHA = 0) SCK0/1 (CPOL = 0) SCK0/1 (CPOL = 1) SPI1/2_DATAIO or SPI1/2_DATAIN or Fig 21. SPI master timing (CPHA = 1) ...
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NXP Semiconductors Fig 22. SPI slave timing (CPHA = 0) SCK0/1 (CPOL = 0) SCK0/1 (CPOL = 1) SPI1/2_DATAIO or SPI1/2_DATAIN or Fig 23. SPI slave timing (CPHA = 1) LPC3220_30_40_50_1 Product data sheet T SPICYC SPI1/2_CLK or SCK0/1 (CPOL ...
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... NXP Semiconductors 12. Package outline TFBGA296: plastic thin fine-pitch ball grid array package; 296 balls ball A1 index area ball index area DIMENSIONS (mm are the original dimensions) A UNIT max 0.4 0.80 0.5 15.1 mm 1.2 0.3 0.65 0.4 14.9 OUTLINE VERSION IEC SOT1048-1 Fig 24. Package outline SOT1048-1 (TFBGA296) ...
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NXP Semiconductors 13. Abbreviations Table 20. Abbreviations Acronym ADC AHB AMBA APB BSDL CISC DDR SDRAM DMA DSP ETM FAB FIFO FIQ GPIO I/O IRQ HS IrDA JTAG LCD MAC MIIM OHCI OTG PHY PLL PWM RAM RMII SE0 SDR ...
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NXP Semiconductors Table 20. Abbreviations Acronym UART USB VFP LPC3220_30_40_50_1 Product data sheet …continued Description Universal Asynchronous Receiver/Transmitter Universal Serial Bus Vector Floating Point processor All information provided in this document is subject to legal disclaimers. Rev. 01.03 — 16 ...
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... NXP Semiconductors 14. Revision history Table 21. Revision history Document ID Release date LPC3220_30_40_50_1.03 <tbd> • Modifications: Power supply domain for pins SYSX_IN and SYSX_OUT pins corrected in • Power supply domain for pin VDD_OSC corrected in • Description of DEBUG pin updated in • Document template updated. ...
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... NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on a weakness or default in the customer application/use or the application/use of customer’s third party customer(s) (hereinafter both referred to as “Application”). It is customer’s sole responsibility to check whether the NXP Semiconductors product is suitable and fit for the Application planned ...
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... NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications. 16. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: LPC3220_30_40_50_1 Product data sheet 15.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners ...
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... USB host controller 7.6.3.3 USB OTG controller . . . . . . . . . . . . . . . . . . . . 31 7.6.4 LCD controller 7.6.4.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 7.7 System functions . . . . . . . . . . . . . . . . . . . . . . 33 7.7.1 Interrupt controller . . . . . . . . . . . . . . . . . . . . . 33 7.7.2 Watchdog timer 7.7.2.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 7.7.3 Millisecond timer . . . . . . . . . . . . . . . . . . . . . . . 33 7.7.3.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 7.7.4 Clocking and power control features . . . . . . . 34 7.7.4.1 Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 7.7.4.2 Crystal oscillator . . . . . . . . . . . . . . . . . . . . . . . 34 7.7.4.3 PLLs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 7.7.4.4 Power control modes ...
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... Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 LPC3220/30/40/50 16/32-bit ARM microcontrollers Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2010. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com ...