EA-OEM-306 Embedded Artists, EA-OEM-306 Datasheet
EA-OEM-306
Specifications of EA-OEM-306
Related parts for EA-OEM-306
EA-OEM-306 Summary of contents
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... The NXP LPC3152/3154 combine an 180 MHz ARM926EJ-S CPU core, High-speed USB 2.0 OTG, 192 kB SRAM, NAND flash controller, flexible external bus interface, an integrated audio codec, Li-ion charger, Real-Time Clock (RTC), and a myriad of serial and parallel interfaces in a single chip targeted at consumer, industrial, medical, and communication markets ...
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... NXP Semiconductors Three-channel 10-bit ADC Integrated 4/8/16-bit 6800/8080 compatible LCD interface Integrated audio codec with stereo ADC and Class AB headphone amplifier System functions Dynamic clock gating and scaling Multiple power domains Selectable boot-up: SPI flash, NAND flash, SD/MMC cards, UART, or USB ...
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NXP Semiconductors 3.1 Ordering options Table 2. Ordering options for LPC3152/54 Type number Total NAND SRAM Flash Controller LPC3152FET208 192 kB yes LPC3154FET208 192 kB yes LPC3152_3154 Preliminary data sheet Security High-speed 10-bit engine USB ADC AES channels no Device/ ...
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NXP Semiconductors 4. Block diagram TEST/DEBUG INTERFACE ARM926EJ-S slave INTERRUPT CONTROLLER slave MPMC slave slave MCI SD/SDIO slave AHB TO APB BRIDGE 0 WDT SYSTEM CONTROL CGU IOCONFIG 10-bit ADC EVENT ROUTER RNG OTP TIMER 0/1/2/3 PWM ...
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... FFAST_OUT 13 ADC10B_VDDA33 14 n.c. 17 HP_OUTL - Row C 1 n.c. 2 EBI_D_10 5 mNAND_RYBN1 6 mGPIO10 9 VPP 10 I2C_SDA0 13 ADC10B_GPA1 14 DAC_VDDA33 17 PSU_PLAY - Row D 1 VDDE_IOA 2 EBI_D_11 LPC3152_3154 Preliminary data sheet ball A1 index area LPC3152 LPC3154 002aae464 Transparent top view Table 11 for pin function selection of multiplexed pins. Pin Symbol ...
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... NXP Semiconductors Table 3. Pin allocation table …continued Pin names with prefix m are multiplexed pins. See Pin Symbol Pin Symbol 5 mNAND_RYBN2 6 mGPIO8 9 SPI_CS_IN 10 PWM_DATA 13 n.c. 14 HP_OUTC 17 PSU_VSSA_CLEAN - Row E 1 VSSE_IOA 2 EBI_D_12 14 HP_VREF 15 RSTIN_N Row F 1 n.c. 2 EBI_D_13 14 TDO 15 DAC_VREFN Row G 1 n.c. ...
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NXP Semiconductors Table 3. Pin allocation table …continued Pin names with prefix m are multiplexed pins. See Pin Symbol Pin Symbol 9 I2SRX_WS0 10 UART_RXD 13 GPIO0 14 ADC_VINR 17 UOS_CX1 - Row T 1 USB_DP 2 USB_GNDA 5 mLCD_DB_7 ...
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... Supply PS3 USB analog supply for driver Supply PS3 USB analog supply for PHY Ground CG1 USB analog ground for clean reference for on chip termination resistors Ground CG1 USB analog ground Ground CG1 USB analog ground for clean reference All information provided in this document is subject to legal disclaimers. ...
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... DI / GPIO I:PU DIO1 JTAG mode select input DO Z DIO2 JTAG data output DI / GPIO I DIO1 UART Clear-To-Send (CTS) (active LOW GPIO O DIO1 UART Ready-To-Send (RTS) (active LOW GPIO I DIO1 UART serial input DO / GPIO O DIO1 UART serial output 2 DIO I IICD I C-bus data line ...
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... Peripheral ground Ground PG2 Analog die peripheral ground DO O DIO4 LCD chip select (active LOW DIO4 LCD: 6800 enable, 8080 read enable (active HIGH DIO4 LCD: instruction register (LOW)/ data register (HIGH) select DO O DIO4 LCD: 6800 read/write select,8080 write enable (active HIGH) ...
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NXP Semiconductors Table 4. Pin description …continued Pin names with prefix m are multiplexed pins. See TFBGA pin name TFB Digital GA I/O ball level [1] [4] I2SRX_BCK0 T9 SUP3 [4] I2SRX_WS0 R9 SUP3 2 I S/Digital audio output [4] ...
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... Cell type Description [3] function state after [2] reset DIO I DIO4 EBI Data I/O 14 DIO I DIO4 EBI Data I DIO4 EBI read enable (active LOW DIO4 EBI write enable (active LOW DIO4 EBI chip enable DIO4 EBI chip enable DIO4 EBI chip enable DIO4 ...
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... The polyfuses get unintentionally burned at random if VPP is powered to 2 greater before the VDDI is powered up to minimum nominal voltage. This will destroy the sample, and it can be locked (security) and the AES key can be corrupted. For this reason it is recommended that VPP be powered by SUP1 at power-on. ...
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... Peripheral supply for NAND flash interface PSU_VBUS, CHARGE_VBUS, USB VBUS voltage UOS_VBUS, USB_VBUS RTC_VDD36, PSU_VBAT1, Li-ion battery voltage PSU_VBAT2, PSU_VBAT RTC_BACKUP Real-time clock voltage domain (generated internally from SUP6) VDDE_IOB Peripheral supply for SDRAM/SRAM/bus-based LCD Section 6.28.3.). Description Bidirectional 3.3 V; 3-state output slew rate control; plain input ...
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... The ARM926EJ-S is intended for multi-tasking applications where full memory management, high performance, and low power are important. This module has the following features: • ARM926EJ-S processor core which uses a five-stage pipeline consisting of fetch, decode, execute, memory and write stages. The processor supports both the 32-bit ARM and 16-bit Thumb instruction sets, which allows a trade off between high performance and high code density ...
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... APB0 domain reserved 128 kB ROM reserved 96 kB ISRAM1 96 kB ISRAM0 reserved shadow area 0 GB (1) AES is available on the LPC3154 only. Fig 3. LPC3152/3154 memory map 6.2.1 Analog die memory organization The blocks on the analog die (Audio codec, RTC, Li-ion charger, and Power Supply Unit ...
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... Before data is written from the buffer to the NAND flash, optionally it is first protected by an error correction code generated by the ECC module. After data is read from the NAND flash, the error correction module corrects errors, and/or the AES decryption module can decrypt data ...
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... AES decoder available on LPC3154 only. Fig 4. Block diagram of the NAND flash controller This module has the following features: • Dedicated NAND flash interface with hardware controlled read and write accesses. • Wear leveling support with 516-byte mode. • Software controlled command and address transfers to support wide range of flash devices. • ...
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... MPMC. This enables the MPMC registers to be situated in memory with other system peripheral registers. • Low transaction latency. • Read and write buffers to reduce latency and to improve performance, particularly for un-cached processors. • Static memory features include: – asynchronous page mode read – ...
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... SD/MMC boot mode. • Contains pre-defined MMU table (16 kB) for simple systems. The LPC3152 ROM memory has the following features: • Supports non-secure booting from SPI flash, NAND flash, SD/SDHC/MMC cards, UART, and USB (DFU class) interfaces. ...
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... UART Test [1] For security reasons this mode is disabled when JTAG security feature is used. 6.8 Internal RAM memory The ISRAM (Internal Static Memory Controller) module is used as controller between the AHB bus and the internal RAM memory. The internal RAM memory can be used as ...
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... Secure Digital (SD) and Multi-Media Card (MMC) standards. The host controller can be used to interface to small form factor expansion cards compliant to the SDIO card standard as well. Finally, the MCI supports CE-ATA 1.1 compliant hard disk drives. This module has the following features: • One 8-bit wide interface. ...
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... The DMA controller has 12 channels. • Scatter-gather is used to gather data located at different areas of memory. Two channels are needed per scatter-gather action. • Supports byte, half word and word transfers, and correctly aligns it over the AHB bus. ...
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... ARM core. The ARM core supports two distinct levels of priority on all interrupt sources, FIQ for high priority interrupts and IRQ for normal priority interrupts. • Software interrupt request capability associated with each request input. • Visibility of interrupts request state before masking. ...
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... ARM DMA 926EJ-S master MULTI-LAYER AHB MATRIX = master/slave connection supported by matrix (1) AES decryption engine is available on LPC3154 only. Fig 5. LPC3152/3154 AHB multi-layer matrix connections This module has the following features: LPC3152_3154 Preliminary data sheet USB-OTG AHB MASTER 3 slave 0 AHB-APB 0 BRIDGE 0 EVENT ROUTER ...
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... The structure of the CGU is shown in belongs to one of the domains. Each clock domain is fed by a single base clock that originates from one of the available clock sources. Within a clock domain, fractional dividers are available to divide the base clock to a lower frequency. ...
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... Each clock generated by the CGU is derived from one of the base clocks and optionally divided by a fractional divider. – Each base clock can be programmed to have any one of the clock sources as an input clock. – Fractional dividers can be used to divide a base clock by a fractional number to a lower clock frequency. – ...
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... The Watchdog Timer can be used to generate a system reset if there is a CPU/software crash. In addition the watchdog timer can be used as an ordinary timer. how the Watchdog Timer module is connected in the system. This module has the following features: • In the event of a software or hardware failure, generates a chip-wide reset request when its programmed time-out period has expired (output m1). • ...
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... Analog-to-Digital Converter (ADC10B) This module is a 10-bit successive approximation Analog-to-Digital Converter (ADC) with an input multiplexer to allow for multiple analog signals on its input. A common use of this module is to read out multiple keys on one input from a resistor network. This module has the following features: • ...
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... Direct events will disappear when the input becomes inactive. • Latched events will remain active until they are explicitly cleared. • Each input can be masked globally for all inputs at once. • Each input can be masked for each output individually. • Event detect status can be read for each output separately. ...
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... ID which is pre-programmed in the wafer fab. – 40 bit are used for security and other features which are programmed at the customer production line. – 184 bit are available for customer use. ...
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... Texas Instruments SSI (Synchronous Serial Interface) frame format with a word size of 4 bit to 16 bit. • Receive FIFO and transmit FIFO of 64 half-words each. • Serial clock rate master mode maximum 45 MHz. • Serial clock rate slave mode maximum 25 MHz. ...
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... Twelve 8 bit slots in a frame with enabling control per slot. • Internal frame clock generation in master mode. • Receive and transmit DMA handshaking using a request/clear protocol. • Interrupt generation per frame. PCM is a very common method used for transmitting analog data in digital format. Most common applications of PCM are digital audio as in audio CDs and computers, digital telephony, and digital videos ...
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... I2STX_0 output and the PCM interface. The pin interface multiplexing is subdivided into five categories: storage, video, audio, NAND flash, and UART related pin multiplexing. Each category supports several modes, which can be selected by programming the corresponding registers in the SysCReg. 6.28.1 Pin connections Table 11 ...
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NXP Semiconductors Table 11. Pin descriptions of multiplexed pins Pin name Default signal mLCD_DB_3 LCD_DB_3 mLCD_DB_4 LCD_DB_4 mLCD_DB_5 LCD_DB_5 mLCD_DB_6 LCD_DB_6 mLCD_DB_7 LCD_DB_7 mLCD_DB_8 LCD_DB_8 mLCD_DB_9 LCD_DB_9 mLCD_DB_10 LCD_DB_10 mLCD_DB_11 LCD_DB_11 mLCD_DB_12 LCD_DB_12 mLCD_DB_13 LCD_DB_13 mLCD_DB_14 LCD_DB_14 mLCD_DB_15 LCD_DB_15 Storage ...
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NXP Semiconductors Table 11. Pin descriptions of multiplexed pins Pin name Default signal mLCD_DB_3 LCD_DB_3 mLCD_DB_4 LCD_DB_4 mLCD_DB_5 LCD_DB_5 mLCD_DB_6 LCD_DB_6 mLCD_DB_7 LCD_DB_7 mLCD_DB_8 LCD_DB_8 mLCD_DB_9 LCD_DB_9 mLCD_DB_10 LCD_DB_10 mLCD_DB_11 LCD_DB_11 mLCD_DB_12 LCD_DB_12 mLCD_DB_13 LCD_DB_13 mLCD_DB_14 LCD_DB_14 mLCD_DB_15 LCD_DB_15 Storage ...
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... MCI_DAT_6 NAND_RYBN2 — NAND flash controller Read/Not busy signal 2. MCI_DAT_6 — MCI card data input/output line 6. MCI_DAT_7 NAND_RYBN3 — NAND flash controller Read/Not busy signal 3. MCI_DAT_7 — MCI card data input/output line 7. PCM_DA I2STX_DATA0 — I2S interface 0 transmit data signal. PCM_DA — PCM serial data line A. ...
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NXP Semiconductors control NAND_NCS_[0:3] control NAND_RYBN[0:3] NAND FLASH INTERFACE control EBI_NCAS_BLOUT_0 3 EBI_NRAS_BLOUT_1 EBI_DQM_0_NOE MPMC LCD Fig 9. Diagram of LCD and MPMC multiplexing Figure 9 only shows the signals that are involved in pad-muxing, so not all interface signals ...
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... Free-running timer: The timer generates an interrupt when the counter reaches zero. The timer wraps around to 0xFFFF FFFF and continues counting down. – Periodic timer: The timer generates an interrupt when the counter reaches zero. It reloads the value from a load register and continues counting down from that value ...
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NXP Semiconductors • Audio codec on the analog die (see – Class AB amplifier – Stereo Analog-to-Digital Converter (SADC) – analog inputs/outputs – Analog Volume Control (AVC) – Stereo Digital-to-Analog Converter (SDAC) • and I LPC3152/3154 ANALOG ...
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... Functional description of the analog die blocks 7.1 Analog die The analog die part of the LPC3152/3154 contains the audio codec, the Real-Time Clock (RTC), the Power Supply Unit (PSU), the Li-ion charger, and the USB charge pump. LPC3152_3154 Preliminary data sheet All information provided in this document is subject to legal disclaimers ...
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... Stereo Digital-to-Analog Converter (SDAC) The Stereo Digital-to-Analog Converter converts a digital audio signal into an analog audio signal. The output of this module is connected to the input of the class AB headphone amplifier. This module has the following features: • Stereo Digital-to-Analog converter with support for 24-bit audio samples. • ...
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... Converter (SADC) or from the analog bypass from the tuner input (through the Analog Volume Control (AVC) block). The class AB amplifier offers a solution in cases where high output levels are required or when the headphone wire is also used as an antenna for tuner reception. This module has the following features: • ...
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... Supported audio sample frequencies are 8 kHz to 55 kHz. • Oversampling rate 128 times the sample frequency. • High dynamic range. • Digital dB-linear volume control in 0.5 dB steps. • DC blocking filter (optional). • Soft start-up. • Mute and overflow detection. 7.3 Li-ion charger The built-in charger allows a Li-ion battery to be charged from the power supplied by a USB connection adapter ...
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... The nominal charge current is programmed with an external program-resistor. This allows the charge current to be adapted to the USB enumeration. • Uses a widespread method to charge a Li-ion battery with the following stages: – Trickle charging with a small current for an (almost) empty battery. – Fast charging in Constant Current mode (CC mode) to the maximum battery voltage of 4.2 V ± ...
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... SUP1 PSU_VOUT3 SUP4/8 1.8 V MODE Fig 13. LPC3152/3154 supply voltages of the analog and digital die This module has the following features: • Takes power from the Li-Ion battery or the USB power supply. • Outputs in Li-Ion battery mode: – PSU_VOUT1, 2 3.2 V (software programmable in 8 levels), 100 mA (analog power supply and I/O). – ...
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... Provides ‘Supply_OK’ detection connected to the system reset signal. 7.6 Real-Time Clock (RTC) The Real-Time Clock module keeps track of the actual date and time, also when the system is switched off. Advanced Digital Rights Management (DRM) schemes require a secure and accurate real-time clock for managing rights such as time-limited playback rights ...
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... The following applies to the limiting values: a) This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static charge. Nonetheless suggested that conventional precautions be taken to avoid applying greater than the rated maximum. b) Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to V otherwise noted ...
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... Preliminary data sheet Conditions Min on pin VDDA12; for 1.0 12 MHz oscillator (SUP1) on pin 2.7 ADC10B_VDDA33; for 10-bit ADC (SUP 3) on pin VPP; write 3.0 on pin VPP; read 1.1 on pin USB_VBUS - (SUP5) on pin USB_VDDA33 3.0 (SUP 3) on pin 2.7 USB_VDDA33_DRV (SUP 3); driver on pin 1 ...
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NXP Semiconductors Table 13: Static characteristics − ° ° +85 C unless otherwise specified. amb Symbol Parameter C input capacitance i Output pins and I/O pins configured as output V output voltage O V HIGH-level ...
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... On pin ADC10B_GNDA. [2] Conditions pin ADC10B_GNDA, V SSA [3] The ADC is monotonic, there are no missing codes. [4] The differential linearity error ( the difference between the actual step width and the ideal step width. See D LPC3152_3154 Preliminary data sheet Conditions Min ...
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... NXP Semiconductors [5] The integral non-linearity ( the peak difference between the center of the steps of the actual and the ideal transfer curve after L(adj) appropriate adjustment of gain and offset errors. See [6] The offset error ( the absolute difference between the straight line which fits the actual curve and the straight line which fits the O ideal curve ...
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... E O (1) Example of an actual transfer curve. (2) The ideal transfer curve. (3) Differential linearity error ( (4) Integral non-linearity (E ). L(adj) (5) Center of a step of the actual transfer curve. Fig 14. ADC characteristics LPC3152_3154 Preliminary data sheet (2) (1) (5) (4) (3) 1 LSB (ideal) 1018 1019 ...
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NXP Semiconductors Fig 15. Suggested 10-bit ADC interface 9.2 Analog die Table 15. Static characteristics of the analog die supply pins − ° ° +85 C unless otherwise specified. amb Symbol Parameter V input/output supply ...
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NXP Semiconductors Table 16: Static characteristics of the PSU − ° ° +85 C unless otherwise specified. amb Symbol Parameter output PSU_VOUT2 V output voltage O ΔV output voltage deviation o I output current O ...
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... ADC; - normal operation per mono ADC; - normal operation - - - for all - modules on; normal operation - In a bandwidth 28 between 300 Hz and 5 kHz. headphone and - DAC headphone - step size 1.071 mA 1.396 mA All information provided in this document is subject to legal disclaimers. Rev. 0.12 — 27 May 2010 ...
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NXP Semiconductors Table 18. Efficiency of output on PSU_VOUT1 (PSU_VOUT1 programmed to 2. BAT on pin PSU_VBAT 2 2.8 3.598 4.396 5.195 5.994 6.793 7.59 8.388 9.231 13.32 17.368 25.59 9.2.1.2 PSU_VOUT2 efficiency 100 η (%) ...
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NXP Semiconductors Table 19. Efficiency of output on PSU_VOUT2 (PSU_VOUT2 programmed to 1. BAT on pin PSU_VBAT 1.002 1.357 1.71 2.063 2.415 2.77 3.122 3.472 3.822 4.172 5.7 7.292 10.466 LPC3152_3154 Preliminary data sheet V / ...
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NXP Semiconductors 9.2.2 Li-ion charger Table 20: Static characteristics of the Li-ion charger Symbol Parameter V battery voltage bat I load current load constant-current charge (fast charge) mode I battery current bat trickle charge mode V battery trickle charge threshold ...
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... Symbol Parameter t address set-up time su(A) t address hold time h(A) t access cycle time cy(a) t write enable pulse width w(en)W t read enable pulse width w(en)R t rise time r t fall time f t data input set-up time su(D) t data input hold time h(D) t ...
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... Typ Max Unit 1 × LCDCLK - - ns 2 × LCDCLK - - ns 5 × LCDCLK [ <tbd> <tbd> −1 × LCDCLK - - ns 2 × LCDCLK - - ns 2 × LCDCLK - - ns 2 × LCDCLK - - ns t h(A) t h(D) read access t dis(Q) write access 002aae208 © NXP B.V. 2010. All rights reserved ...
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... Timing is determined by the LCD Interface Control Register fields SERIAL_CLK_SHIFT = 3; SERIAL_READ_POS = 3. See the LPC315x user manual. mLCD_CSB mLCD_RS mLCD_DB13 (serial clock) mLCD_DB14 (serial data in) mLCD_DB15 (serial data out) Fig 20. LCD timing (serial mode) ...
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... Dynamic characteristics: static external memory interface − ° ° pF +85 C, unless otherwise specified amb Symbol Parameter Common to read and write cycles t CS LOW to address valid CSLAV time Read cycle parameters t OE LOW to address valid OELAV time t BLS LOW to address valid BLSLAV time ...
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... NXP Semiconductors EBI_NSTCS_X t CSLAV EBI_A_[15:0] EBI_DQM_0_NOE t t EBI_NCAS_BLOUT_0 EBI_NRAS_BLOUT_1 t EBI_D_[15:0] Fig 21. External memory read access to static memory LPC3152_3154 Preliminary data sheet t OELAV t OELOEH CSLOEL BLSLAV t BLSLBLSH CSLBLSL All information provided in this document is subject to legal disclaimers. Rev. 0.12 — 27 May 2010 LPC3152/3154 ...
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NXP Semiconductors EBI_NSTCS_X EBI_A_[15:0] EBI_D_[15:0] EBI_NWE EBI_NCAS_BLOUT_0 EBI_NRAS_BLOUT_1 Fig 22. External memory write access to static memory 10.1.3 SDRAM controller Table 25. Dynamic characteristics of SDR SDRAM memory interface − ° ° +85 C, unless ...
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... Parameters are valid over operating temperature range unless otherwise specified. All values valid for pads set to high slew rate. VDDE_IOA = VDDE_IOB = 1.8 ± 0.15 V. VDDI = 1.2 ± 0.1 V. [2] [3] Refer to the LPC3152/3154 user manual for the programming of MPMCDynamicReadConfig and SYSCREG_MPMP_DELAYMODES registers. [4] f ...
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... NXP Semiconductors T CLCL t CHCX EBI_CLKOUT EBI_NRAS_BLOUT EBI_NCAS_BLOUT EBI_NWE EBI_CKE EBI_NDYCS EBI_DQMx EBI_A_[15:2] EBI_D_[15:0] EBI_CKE is HIGH. Fig 23. SDRAM burst read timing LPC3152_3154 Preliminary data sheet t CLCX t t d(o) h(o) READ NOP NOP NOP t d(o) t h(A) BANK su(D) h(D) COLUMN DATA n CAS DATA n+1 LATENCY = 2 All information provided in this document is subject to legal disclaimers ...
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T CLCL t CLCX t CHCX EBI_CLKOUT EBI_CKE EBI_NRAS_BLOUT EBI_NCAS_BLOUT EBI_NWE EBI_CKE EBI_NDYCS EBI_DQMx EBI_A_[15:2] EBI_D_[15:0] Fig 24. SDRAM bank activate and write timing t ...
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... NANDFLASH_NAND_CLK, see LPC315x user manual. HCLK [2] See registers NandTiming1 and NandTiming2 in the LPC315x user manual. [3] Each timing parameter can be set from 7 nand_clk clock cycles to 1 nand_clk clock cycle. (A programmed zero value is treated as a one). Fig 25. NAND flash controller write and read timing LPC3152_3154 Preliminary data sheet ° ...
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NXP Semiconductors 10.2.1 Crystal oscillator Table 27: Dynamic characteristics: crystal oscillator Symbol Parameter f oscillator frequency osc δ clock duty cycle clk C crystal capacitance xtal t start-up time startup P drive power drive 10.2.2 SPI Table 28. Dynamic characteristics ...
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NXP Semiconductors SCK (CPOL = 0) SCK (CPOL = 1) Fig 26. SPI master timing (CPHA = 1) Fig 27. SPI master timing (CPHA = 0) LPC3152_3154 Preliminary data sheet t SPICLK t SPISEDV DATA VALID MOSI MISO DATA VALID ...
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... SCK (CPOL = 1) t MOSI DATA VALID t SPISEDV MISO DATA VALID [1] Conditions Min = 25 ° amb measured in SPI Master mode; see Figure 30 All information provided in this document is subject to legal disclaimers. Rev. 0.12 — 27 May 2010 LPC3152/3154 t t SPICLKH SPICLKL t t SPIDSU SPIDH DATA VALID ...
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NXP Semiconductors shifting edges SCK MOSI MISO Fig 30. MISO line set-up time in SSP Master mode LPC3152_3154 Preliminary data sheet t su(SPI_MISO) All information provided in this document is subject to legal disclaimers. Rev. 0.12 — 27 May 2010 ...
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NXP Semiconductors 2 10.2.3 I S-interface Table 30. Dynamic characteristics: I − ° ° +85 C for industrial applications amb Symbol Parameter common to input and output T clock cycle time cy(clk) t fall time ...
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... HIGH period of the SCL clock HIGH t data set-up time SU;DAT t set-up time for a repeated START SU;STA condition t set-up time for STOP condition SU;STO [1] Parameters are valid over operating temperature range unless otherwise specified. Typical ratings are not guaranteed. The values listed are at room temperature (25 °C), nominal supply voltages. ...
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NXP Semiconductors SDA t t BUF LOW SCL HD;STA Remark: Signals SDA and SCL correspond to pins I2C_SDAx and I2C_SCLx ( 1). 2 Fig 33. I C-bus pins clock timing LPC3152_3154 Preliminary data sheet t ...
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NXP Semiconductors 10.2.5 USB interface Table 32. Dynamic characteristics: USB pins (high-speed) Ω pF 1 DD(IO) Symbol Parameter t rise time r t fall time f t differential ...
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... P output power o (THD+N)/S Total harmonic distortion plus noise-to-signal ratio S/N Signal-to-noise ratio PSRR power supply ripple rejection α channel crosstalk ct(ch) Measured with 20 kHz block filter. [1] Table 35: Dynamic characteristic for analog in − ° ° +85 C unless otherwise specified. amb Symbol ...
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Application information Table 36. LCD panel connections TFBGA pin # Pin name R8 mLCD_CSB/EBI_NSTCS_0 P7 mLCD_E_RD/EBI_CKE R7 mLCD_RS/EBI_NDYCS T8 mLCD_RW_WR/EBI_DQM_1 T7 mLCD_DB_0/EBI_CLKOUT P8 mLCD_DB_1/EBI_NSTCS_1 ...
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NXP Semiconductors 12. Marking Table 37. LPC3152/3154 Marking Line A LPC3152_3154 Preliminary data sheet Marking Description LPC3152/3154 BASIC_TYPE All information provided in this document is subject to legal disclaimers. Rev. 0.12 — 27 May 2010 LPC3152/3154 © NXP B.V. 2010. ...
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... NXP Semiconductors 13. Package outline TFBGA208: plastic thin fine-pitch ball grid array package; 208 balls; body 0.7 mm ball A1 index area ball index area DIMENSIONS (mm are the original dimensions) A UNIT max 0.35 0.80 0.45 12.1 mm 1.15 0.25 0.65 0.35 11.9 OUTLINE VERSION IEC SOT930-1 Fig 35 ...
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... Direct Memory Access Controller Digital Rights Management Error Correction Code Finite Input Response Headphones Input Output Configuration Read Only Memory Infrared Data Association Joint Test Action Group Internal Static RAM Memory Joint Test Action Group Liquid Crystal Display Low Drop voltage Output regulator ...
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NXP Semiconductors Table 38: Abbreviations Acronym Timer UART USB 2.0 HS OTG Universal Serial Bus 2.0 High-Speed On-The-Go LPC3152_3154 Preliminary data sheet …continued Description Timer module Universal Asynchronous Receiver Transmitter All information provided in this document is subject to legal ...
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... NXP Semiconductors 15. Revision history Table 39: Revision history Document ID Release date LPC3152_3154 v.0.12 <tbd> • Modifications: Reset state of JTAG pins and GPIO0, GPIO1, and GPIO2 pins updated in • Document template updated. • Digital I/O level for pin CLOCK_OUT corrected in • USB Hi-speed logo added. ...
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... NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’ ...
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... Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: LPC3152_3154 Preliminary data sheet whenever customer uses the product for automotive applications beyond NXP Semiconductors’ specifications such use shall be solely at customer’s ...
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... NXP Semiconductors 18. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 2.1 Key features . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 3.1 Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 3 4 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4 5 Pinning information . . . . . . . . . . . . . . . . . . . . . . 5 5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 6 Functional description . . . . . . . . . . . . . . . . . . 16 6.1 ARM926EJ 6.2 Memory map 6.2.1 Analog die memory organization . . . . . . . . . . 17 6.3 JTAG ...
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... Contact information Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 LPC3152/3154 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2010. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Document identifier: LPC3152_3154 All rights reserved ...