TOOLSTICK540DC Silicon Laboratories Inc, TOOLSTICK540DC Datasheet - Page 192
TOOLSTICK540DC
Manufacturer Part Number
TOOLSTICK540DC
Description
DAUGHTER CARD TOOLSTICK F540
Manufacturer
Silicon Laboratories Inc
Series
ToolStickr
Type
MCUr
Datasheets
1.TOOLSTICK540DC.pdf
(274 pages)
2.TOOLSTICK540DC.pdf
(16 pages)
3.TOOLSTICK540DC.pdf
(12 pages)
Specifications of TOOLSTICK540DC
Contents
Daughter Card
Processor To Be Evaluated
C8051F54x
Processor Series
C8051F54x
Interface Type
USB
Operating Supply Voltage
2.7 V to 3.6 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With/related Products
C8051F54x
For Use With
336-1345 - TOOLSTICK BASE ADAPTER336-1182 - ADAPTER USB DEBUG FOR C8051FXXX
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1717
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C8051F54x
meet the SMBus Specification requirements of 250 ns and 300 ns, respectively. Table 20.2 shows the min-
imum setup and hold times for the two EXTHOLD settings. Setup and hold time extensions are typically
necessary when SYSCLK is above 10 MHz.
With the SMBTOE bit set, Timer 3 should be configured to overflow after 25 ms in order to detect SCL low
timeouts (see Section “20.3.4. SCL Low Timeout” on page 189). The SMBus interface will force Timer 3 to
reload while SCL is high, and allow Timer 3 to count when SCL is low. The Timer 3 interrupt service routine
should be used to reset SMBus communication by disabling and re-enabling the SMBus.
SMBus Free Timeout detection can be enabled by setting the SMBFTE bit. When this bit is set, the bus will
be considered free if SDA and SCL remain high for more than 10 SMBus clock source periods (see
Figure 20.4).
192
*Note: Setup Time for ACK bit transmissions and the MSB of all data transfers. When using
EXTHOLD
software acknowledgement, the s/w delay occurs between the time SMB0DAT or
ACK is written and when SI is cleared. Note that if SI is cleared in the same write
that defines the outgoing ACK value, s/w delay is zero.
0
1
Table 20.2. Minimum SDA Setup and Hold Times
T
or
1 system clock + s/w delay
11 system clocks
low
Minimum SDA Setup Time
– 4 system clocks
Rev. 1.1
*
3 system clocks
12 system clocks
Minimum SDA Hold Time
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